New interconnect plasma induced damage analyzed by flash memory cell array (English)
- New search for: Takebuchi, M.
- New search for: Yamada, K.
- New search for: Nishimura, T.
- New search for: Isobe, K.
- New search for: Uemura, T.
- New search for: Fujimoto, T.
- New search for: Arakawa, M.
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- New search for: Yoshikawa, K.
- New search for: Takebuchi, M.
- New search for: Yamada, K.
- New search for: Nishimura, T.
- New search for: Isobe, K.
- New search for: Uemura, T.
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- New search for: Arakawa, M.
- New search for: Mori, S.
- New search for: Kimitsuka, A.
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In:
International Electron Devices Meeting. Technical Digest
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185-188
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1996
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ISBN:
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ISSN:
- Conference paper / Electronic Resource
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Title:New interconnect plasma induced damage analyzed by flash memory cell array
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Contributors:Takebuchi, M. ( author ) / Yamada, K. ( author ) / Nishimura, T. ( author ) / Isobe, K. ( author ) / Uemura, T. ( author ) / Fujimoto, T. ( author ) / Arakawa, M. ( author ) / Mori, S. ( author ) / Kimitsuka, A. ( author ) / Yoshikawa, K. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:1996-01-01
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Size:379173 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_3
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International Electron Devices Meeting. Technical Digest [Front Matter and Table of Contents]| 1996
- 3
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SOI: materials to systemsAuberton-Herve, A.J. et al. | 1996
- 11
-
Microelectromechanical systems: interfacing electronics to a non-electronic worldWise, K.D. et al. | 1996
- 19
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Foundry technologiesTseng, F.C. et al. | 1996
- 27
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Recent Advances in III-V Nitride Electron Devices (Invited Paper)Asif Khan, M. / Chen, Q. / Yang, J. / Anwar, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 27
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Recent advances in III-V nitride electron devicesKhan, M.A. / Chen, Q. / Yang, J. / Anwar, M.Z. / Blasingame, M. / Shur, M.S. / Burm, J. / Eastman, L.F. et al. | 1996
- 31
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Potential profile measurement of cleaved surface of GaAs HEMTs by Kelvin probe force microscopyMizutani, T. / Arakawa, M. / Kishimoto, S. et al. | 1996
- 35
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A model for tunneling-limited breakdown in high-power HEMTsSomerville, M.H. / del Alamo, J.A. et al. | 1996
- 39
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High temperature operation of AlInAs/InGaAs/AlInAs 3D-SMODFETs with record two-dimensional electron gas densitiesMartint, G.H. / Lepore, A. / Pereiaslavets, B. / Spencer, R.M. / Eastman, L.F. et al. | 1996
- 43
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Effects of channel quantization and temperature on off-state and on-state breakdown in composite channel and conventional InP-based HEMTsMeneghesso, G. / Mion, A. / Neviani, A. / Matloubian, M. / Brown, J. / Hafizi, M. / Takyiu Liu, / Canali, C. / Pavesi, M. / Manfredi, M. et al. | 1996
- 47
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Control of electro-chemical etching for uniform 0.1 /spl mu/m gate formation of HEMTNitta, Y. / Ohshima, T. / Shigemasa, R. / Nishi, S. / Kimura, T. et al. | 1996
- 47
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Control of Electro-Chemical Etching for Uniform 0.1 m Gate Formation of HEMTNitta, Y. / Ohshima, T. / Shigemasa, R. / Nishi, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 51
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Monolithic integration of InAlAs/InGaAs/InP enhancement- and depletion-mode high electron mobility transistorsMahajan, A. / Fay, P. / Arafa, M. / Cueva, G. / Adesida, I. et al. | 1996
- 57
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Lithography Prospects for 0.181 m Technology and Beyond, (Invited Paper)Okazaki, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 57
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Lithography prospects for 0.18-/spl mu/m technology and beyondOkazaki, S. et al. | 1996
- 61
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0.12 /spl mu/m hole pattern formation by KrF lithography for Giga bit DRAMNakao, S. / Nakae, A. / Yamaguchi, A. / Kimura, H. / Ohno, Y. / Matsui, Y. / Hirayama, M. et al. | 1996
- 61
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0.12 m Hole Pattern Formation by KrF Lithography for Giga Bit DRAMNakao, S. / Nakae, A. / Yamaguchi, A. / Kimura, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 65
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The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metalBanerjee, K. / Amerasekera, A. / Dixit, G. / Chenming Hu, et al. | 1996
- 69
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An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) techniqueChen, J.C. / McGaughy, B.W. / Sylvester, D. / Chenming Hu, et al. | 1996
- 73
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Modeling of local reduction in TiSi/sub 2/ and CoSi/sub 2/ growth near spacers in MOS technologies: influence of mechanical stress and main diffusing speciesFornara, P. / Poncet, A. et al. | 1996
- 73
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Modeling of Local Reduction in TiSi~2 and CoSi~2 Growth Near Spacers in MOS Technologies: Influence of Mechanical Stress end Main Diffusing SpeciesFornara, P. / Poncet, A. / Institute of Electrical and Electronics Engineers et al. | 1996
- 77
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The impact of mechanical stress control on VLSI fabrication processIkeda, S. / Hagiwara, Y. / Miura, H. / Ohta, H. et al. | 1996
- 83
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High efficiency 2 GHz power Si-MOSFET design under low supply voltage down to 1 VOhguro, T. / Saito, M. / Morifuji, E. / Murakami, K. / Matsuzaki, K. / Yoshitomi, T. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1996
- 87
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High performance silicon LDMOS technology for 2 GHz RF power amplifier applicationsWood, A. / Dragon, C. / Burger, W. et al. | 1996
- 91
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High efficiency LDMOS power FET for low voltage wireless communicationsMa, G. / Burger, W. / Dragon, C. / Gillenwater, T. et al. | 1996
- 95
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A sealed cavity TFR process for RF bandpass filtersLutsky, J.J. / Naik, R.S. / Reif, R. / Sodini, C.G. et al. | 1996
- 99
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Monolithic Spiral Inductors Fabricated Using VLSI Cu-Damascene Interconnect Technology and Low-Loss SubstratesBurghartz, J. / Edelstein, D. / Jenkins, K. / Jahnes, C. / Institute of Electrical and Electronics Engineers et al. | 1996
- 99
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Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substratesBurghartz, J.N. / Edelstein, D.C. / Jenkins, K.A. / Jahnes, C. / Uzoh, C. / O'Sullivan, E.J. / Chan, K.K. / Soyuer, M. / Roper, P. / Cordes, S. et al. | 1996
- 105
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High-frequency AC characteristics of 1.5 nm gate oxide MOSFETsMomose, H.S. / Morifuji, E. / Yoshitomi, T. / Saito, I. / Morimoto, T. / Katsumata, Y. / Iwai, H. et al. | 1996
- 109
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Experimental study of carrier velocity overshoot in sub-0.1 /spl mu/m devices-physical limitation of MOS structuresMizuno, T. / Ohba, R. et al. | 1996
- 109
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Experimental Study of Carrier Velocity Overshoot in Sub-0.1m Devices-Physical Limitation of MOS StructuresMizuno, T. / Ohba, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 113
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Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFETWann, C. / Assaderaghi, F. / Dennard, R. / Chenming Hu, / Shahidi, G. / Taur, Y. et al. | 1996
- 117
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Reliable tantalum gate fully-depleted-SOI MOSFETs with 0.15 /spl mu/m gate length by low-temperature processing below 500/spl deg/CUshikil, T. / Mo Chiun Yu, / Hirano, Y. / Shimada, H. / Morita, M. / Ohmi, T. et al. | 1996
- 117
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Reliable Tantalum Gate Fully-Depleted-SOI MOSFETs with 0.15 m Gate Length by Low-Temperature Processing Below 500CUshiki, T. / Yu, M. C. / Hirano, Y. / Shimada, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 121
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BESS: a source structure that fully suppresses the floating body effects in SOI CMOSFETsHoriuchi, M. / Tamura, M. et al. | 1996
- 125
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Effect of body-charge on fully- and partially-depleted SOI MOSFET designSherony, M.J. / Wei, A. / Antoniadis, D.A. et al. | 1996
- 129
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Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuitsMaeda, S. / Yamaguchi, Y. / Kim, I.-J. / Iwamatsu, T. / Ipposhi, T. / Miyamoto, S. / Maegawa, S. / Ueda, K. / Nii, K. / Mashiko, K. et al. | 1996
- 133
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Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-mode applicationsBabcock, J.A. / Huang, W.M. / Ford, J.M. / Ngo, D. / Spooner, D.J. / Cheng, S. et al. | 1996
- 139
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A physically-based built-in Spice poly-Si TFT model for circuit simulation and reliability evaluationChung, S.S. / Chen, D.C. / Cheng, C.T. / Yeh, C.F. et al. | 1996
- 143
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A Continuous Compact MOSFET Model for SOI with Automatic Transitions Between Fully and Partially Depleted Device BehaviourSleight, J. / Rios, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 143
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A continuous compact MOSFET model for SOI with automatic transitions between fully and partially depleted device behaviorSleight, J.W. / Rios, R. et al. | 1996
- 147
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A new physics-based, predictive compact model for small-geometry MOSFET's including two-dimensional calculations with a close link to process and layout dataKlos, A. / Kostka, A. et al. | 1996
- 151
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A CAD-compatible non-quasi-static MOSFET modelLiu, W. / Bowen, C. / Mi-Chang Chang, et al. | 1996
- 155
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A physical model for planar spiral inductors on siliconYue, C.P. / Ryu, C. / Lau, J. / Lee, T.H. / Wong, S.S. et al. | 1996
- 159
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Multifinger Effect in GaAs FET Distributed Large Signal CAD ModelAvitabile, G. / Cidronali, A. / Vannini, G. / Manes, G. / Institute of Electrical and Electronics Engineers et al. | 1996
- 159
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Multifinger effect in a GaAs FET distributed large signal CAD modelAvitabile, G. / Cidronali, A. / Vannini, G. / Manes, G. et al. | 1996
- 163
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Distortion Analysis of GaAs MESFETs Based on Physical Model Using PlSCES-HBSato-lwanaga, J. / Fujimoto, K. / Masato, H. / Ota, Y. / Institute of Electrical and Electronics Engineers et al. | 1996
- 163
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Distortion analysis of GaAs MESFETs based on physical model using PISCES-HBSato-Iwanaga, J. / Fujimoto, K. / Masato, H. / Ota, Y. / Inoue, K. / Troyanovsky, B. / Yu, Z. / Dutton, R.W. et al. | 1996
- 169
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Multilevel flash cells and their trade-offsEitan, B. / Kazerounian, R. / Roy, A. / Crisenza, G. / Cappelletti, P. / Modelli, A. et al. | 1996
- 169
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Multilevel FLASH Cells and Their Trade-Offs, (Invited Paper)Eitan, B. / Kazerounian, R. / Roy, A. / Crisenza, G. / Institute of Electrical and Electronics Engineers et al. | 1996
- 173
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A New Shared Bit Line NAND Cell Technology for the 256 Mb Flash Memory with 12V ProgrammingShin, W. C. / Choi, J. D. / Kim, D. J. / Kim, J. / Institute of Electrical and Electronics Engineers et al. | 1996
- 177
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A shallow-trench-isolation flash memory technology with a source-bias programming methodKato, M. / Adachi, T. / Tanaka, T. et al. | 1996
- 181
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Novel self-limiting program scheme utilizing N-channel select transistors in P-channel DINOR flash memoryOhnakado, T. / Takada, H. / Hayashi, K. / Sugahara, K. / Satoh, S. / Abe, H. et al. | 1996
- 185
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New interconnect plasma induced damage analyzed by flash memory cell arrayTakebuchi, M. / Yamada, K. / Nishimura, T. / Isobe, K. / Uemura, T. / Fujimoto, T. / Arakawa, M. / Mori, S. / Kimitsuka, A. / Yoshikawa, K. et al. | 1996
- 189
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A novel high-density low-cost diode programmable read only memoryde Graaf, C. / Woerlee, P.H. / Hart, C.M. / Lifka, H. / de Vreede, P.W.H. / Janssen, P.J.M. / Sluijs, F.J. / Paulzen, G.M. et al. | 1996
- 193
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High Density Nonvolatile Magnetorestive RAMTehrani, S. / Chen, E. / Durlam, M. / Zhu, T. / Institute of Electrical and Electronics Engineers et al. | 1996
- 193
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High density nonvolatile magnetoresistive RAMTehrani, S. / Chen, E. / Durlam, M. / Zhu, T. / Goronkin, H. et al. | 1996
- 199
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InP-based HBT technology for millimeter-wave MMIC VCOsCowles, J. / Tran, L. / Wang, H. / Lin, E. / Block, T. / Streit, D. / Oki, A. et al. | 1996
- 203
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Hydrogen-related burn-in in GaAs/AlGaAs HBTs and implications for reliabilityHenderson, T. / Ley, V. / Kim, T. / Moise, T. / Hill, D. et al. | 1996
- 207
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InGaP/GaAs HBT with novel layer structure for emitter ledge fabricationFresina, M.T. / Hartmann, Q.J. / Thomas, S. / Ahmari, D.A. / Caruth, D. / Feng, M. / Stillman, G.E. et al. | 1996
- 211
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A 0.1 m Self-Aligned-Gate GaAs MESFET with Multilayer Interconnection Structure for Ultra-High-Speed ICsTokumitsu, M. / Hirano, M. / Otsuji, T. / Yamaguchi, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 211
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A 0.1-/spl mu/m self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICsTokumitsu, M. / Hirano, M. / Otsuji, T. / Yamaguchi, S. / Yamasaki, K. et al. | 1996
- 215
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A novel fabrication technology for integrating FETs and high-performance diodes, and its application to MMIC VCOJong-Wan Jung, / Young-Se Kwon, et al. | 1996
- 215
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A Novel Fabrication Technology for Integrating FETe and High-Performance Diodes, and its Application to MMIC VCOJune, J.-W. / Kwon, Y.-S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 219
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High temperature MESFET based integrated circuits operating up to 300/spl deg/CWurfl, J. / Janke, B. / Nebauer, E. / Thierbach, S. / Wolter, P. et al. | 1996
- 219
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High Temperature MESFET Based Integrated Circuits Operating up to 300CWuerfl, J. / Janke, B. / Nebauer, E. / Thierbach, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 225
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SiC electronicsAgarwal, A.K. / Augustine, G. / Balakrishna, V. / Brandt, C.D. / Burk, A.A. / Li-Shu Chen, / Clarke, R.C. / Esker, P.M. / Hobgood, H.M. / Hopkins, R.H. et al. | 1996
- 225
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SiC Electronics (Invited Paper)Agarwal, A. / Augustine, G. / Balakrishna, V. / Brandt, C. D. / Institute of Electrical and Electronics Engineers et al. | 1996
- 231
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Recent Progress in Crystal Growth, Conductivity Control and Light Emitters of Group III Nitride Semiconductors (Invited Paper)Akasaki, I. / Amano, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 231
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Recent progress of crystal growth, conductivity control and light emitters of group III nitride semiconductorsAkasaki, I. / Amano, H. et al. | 1996
- 239
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Biomedical applications of MEMSPetersen, K. et al. | 1996
- 239
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Biomedical Applications of MEMs (Invited Paper)Peterson, K. / Institute of Electrical and Electronics Engineers et al. | 1996
- 245
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Sub-10-fJ ECL/68A 4.7-GHz Divider Ultra-Low-Power SiGe Base Bipolar Transistors with a Wedge-Shaped CVD-SiO~2 Isolation Structure and a BPSG-Refilled TrenchKondo, M. / Oda, K. / Ohue, E. / Shimamoto, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 245
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Sub-10-fJ ECL/68-/spl mu/A 4.7-GHz divider ultra-low-power SiGe base bipolar transistors with a wedge-shaped CVD-SiO/sub 2/ isolation structure and a BPSG-refilled trenchKondo, M. / Oda, K. / Ohue, E. / Shimamoto, H. / Tanabe, M. / Onai, T. / Washio, K. et al. | 1996
- 249
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Suppression of boron outdiffusion in SiGe HBTs by carbon incorporationLanzerotti, L.D. / Sturm, J.C. / Stach, E. / Hull, R. / Buyuklimanli, T. / Magee, C. et al. | 1996
- 253
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Impact of profile scaling on high-injection barrier effects in advanced UHV/CVD SiGe HBTsJoseph, A.J. / Cressler, J.D. / Richey, D.M. / Harame, D.L. et al. | 1996
- 257
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Effect of carbon on the valence band offset of Si/sub 1-x-y/Ge/sub x/C/sub y//Si heterojunctionsChang, C.L. / St. Amour, A. / Sturm, J.C. et al. | 1996
- 257
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Effect of Carbon on the Valence Band Offset of Si~1~-~x~-~yGe~xC~y/Si HeterojunctionsChang, C. / St. Armour, A. / Sturm, J. / Institute of Electrical and Electronics Engineers et al. | 1996
- 261
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Novel SiGeC channel heterojunction PMOSFETRay, S.K. / John, S. / Oswal, S. / Banerjee, S.K. et al. | 1996
- 265
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Room temperature negative differential conductance in three-terminal silicon surface tunneling deviceKoga, J. / Toriumi, A. et al. | 1996
- 265
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Room Temperature Negative Differntial Conductance in Three-Terminal Silicon Surface Tunneling DeviceKoga, J. / Toriumi, A. / Institute of Electrical and Electronics Engineers et al. | 1996
- 271
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Advanced SRAM Technology-The Race Between 4T and 6T Cells (Invited Paper)Lage, C. / Hayden, J. / Subramanian, C. / Institute of Electrical and Electronics Engineers et al. | 1996
- 271
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Advanced SRAM technology-the race between 4T and 6T cellsLage, C. / Hayden, J.D. / Subramanian, C. et al. | 1996
- 275
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A High-Density 6.9 sq. m Embedded SRAM Cell in a High-Performance 0.25 m-Generation CMOS Logic TechnologySubbanna, S. / Agnello, R. / Crabbe, E. / Schulz, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 275
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A high-density 6.9 sq. /spl mu/m embedded SRAM cell in a high-performance 0.25 /spl mu/m-generation CMOS logic technologySubbanna, S. / Agnello, P. / Crabbe, E. / Schulz, R. / Wu, S. / Tallman, K. / Saccamango, M.J. / Greco, S. / McGahay, V. / Allen, A.J. et al. | 1996
- 279
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A C-Switch cell for low-voltage operation and high-density SRAMsKuriyama, H. / Ishigaki, Y. / Fujii, Y. / Maegawa, S. / Maeda, S. / Miyamoto, S. / Tsutsumi, K. / Miyoshi, H. et al. | 1996
- 283
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A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operationHayashi, F. / Ohkubo, H. / Takahashi, T. / Horiba, S. / Noda, K. / Uchida, T. / Shimizu, T. / Sugawara, N. / Kumashiro, S. et al. | 1996
- 289
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Molybdenum field-emitter arraysSpindt, C.A. / Brodie, I. et al. | 1996
- 293
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Enhancement of electron emission efficiency and stability of molybdenum field emitter array by diamond-like carbon coatingJung, J.H. / Ju, B.K. / Lee, Y.H. / Oh, M.H. / Jang, J. et al. | 1996
- 297
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Low operation voltage field emitter arrays using low work function materials fabricated by transfer mold techniqueNakamoto, M. / Hasegawa, T. / Ono, T. / Sakai, T. / Sakuma, N. et al. | 1996
- 301
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A novel structure of silicon field emission cathode with sputtered TiW for gate electrode and TEOS oxide for gate dielectricSung Weon Kang, / Jin Ho Lee, / Yoon-Ho Song, / Syoung Gon Yu, / Kyoung Ik Cho, / Hyung Joun Yoo, et al. | 1996
- 305
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A Novel Lateral Field Emitter Trioide with Insitu Vacuum EncapsulationPark, C. M. / Lim, M. S. / Min, B.-H. / Han, M. K. / Institute of Electrical and Electronics Engineers et al. | 1996
- 305
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A novel lateral field emitter triode with insitu vacuum encapsulationCheol-Min Park, / Moo-Sup Lim, / Byung-Hyuk Min, / Min-Koo Han, / Yearn-Ik Choi, et al. | 1996
- 309
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A MOSFET-structured Si tip for stable emission currentHirano, T. / Kanemaru, S. / Itoh, J. et al. | 1996
- 313
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Novel single- and double-gate race-track-shaped field emitter structuresSin, J.K.O. / Cai, J. / Poon, M.C. / Wang, C. / Tong, L. et al. | 1996
- 319
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Gate oxide scaling limits and projectionChenming Hu, et al. | 1996
- 319
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Gate Oxide Scaling Limits and Projection (Invited Paper)Hu, C. / Institute of Electrical and Electronics Engineers et al. | 1996
- 323
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Experimental evidence of inelastic tunneling and new I-V model for stress-induced leakage currentTakagi, S. / Yasuda, N. / Toriumi, A. et al. | 1996
- 327
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A new polarity dependence of the reduced trap generation during high-field degradation of nitrided oxidesDegraeve, R. / De Blauwe, J. / Ogier, J.L. / Roussel, Ph. / Maes, H.E. et al. | 1996
- 331
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Leakage current, reliability characteristics, and boron penetration of ultra-thin (32-36 /spl Aring/) O/sub 2/-oxides and N/sub 2/O/NO oxynitridesChuan Lin, / Chou, A.I. / Kumar, K. / Chowdhury, P. / Lee, J.C. et al. | 1996
- 331
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Leakage Current, Reliability Characteristics and Boron Penetration of Ultra-Thin (32-36) O~2-Oxide and N~2O/NO OxynitridesLin, C. / Chou, A. / Kumar, K. / Chowdhury, P. / Institute of Electrical and Electronics Engineers et al. | 1996
- 335
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High reliability of nanometer-range N/sub 2/O-nitrided oxides due to suppressing hole injectionKobayashi, K. / Teramoto, A. / Nakamura, T. / Watanabe, H. / Kurokawa, H. / Matsui, Y. / Hirayama, M. et al. | 1996
- 335
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High Reliability of Nanometer-Range N~2O-Nitrided Oxides Due to Suppressing Hole InjectionKobayashi, K. / Teramoto, A. / Nakamura, T. / Watanabe, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 339
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Improved performance and reliability of split gate source-side injected flash memory cellsBhattacharya, S. / Lai, K. / Fox, K. / Chan, P. / Worley, E. / Sharma, U. / Liming Hwang, / Li, G.P. et al. | 1996
- 343
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A New Quantitative Model to Predict SILC-Related Disturb characteristics in Flash E^2PROM DevicesDeBlauwe, J. / Van Houdt, J. / Wellekens, D. / Degraeve, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 343
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A new quantitative model to predict SILC-related disturb characteristics in flash E/sup 2/PROM devicesDe Blauwe, J. / Van Houdt, J. / Wellekens, D. / Degraeve, R. / Roussel, P. / Haspeslagh, L. / Groeseneken, G. / Maes, H.E. et al. | 1996
- 349
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Slurry Engineering for Self-Stopping, Dishing Free SiO~2-CMPNojo, H. / Kodera, M. / Nakata, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 349
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Slurry engineering for self-stopping, dishing free SiO/sub 2/-CMPNojo, H. / Kodera, M. / Nakata, R. et al. | 1996
- 353
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A novel low temperature PVD planarized Al-Cu process for high aspect ratio sub-half micron interconnectZhao, B. / Biberger, M.A. / Hoffman, V. / Wang, S.-Q. / Vasudev, P.K. / Seidel, T.E. et al. | 1996
- 357
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Ion Metal Plasma (IMP) Deposited Titanium Liners for 0.25/0.18m Multilevel InterconnectionsDixit, G. / Hsu, W. / Konecni, A. / Krishnan, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 357
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Ion metal plasma (IMP) deposited titanium liners for 0.25/0.18 /spl mu/m multilevel interconnectionsDixit, G.A. / Hsu, W.Y. / Konecni, A.J. / Krishnan, S. / Luttmer, J.D. / Havemann, R.H. / Forster, J. / Yao, G.D. / Narasimhan, M. / Xu, Z. et al. | 1996
- 361
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A novel TiN/Ti contact plug technology for gigabit scale DRAM using Ti-PECVD and TiN-LPCVDOhto, K. / Urabe, K. / Taguwa, T. / Chikaki, S. / Kikkawa, T. et al. | 1996
- 365
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Barrier metal free copper damascene interconnection technology using atmospheric copper reflow and nitrogen doping in SiOF filmMikagi, K. / Ishikawa, H. / Usami, T. / Suzuki, M. / Inoue, K. / Oda, N. / Chikaki, S. / Sakai, I. / Kikkawa, T. et al. | 1996
- 369
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Low-k fluorinated amorphous carbon interlayer technology for quarter micron devicesMatsubara, Y. / Endo, K. / Tatsumi, T. / Ueno, H. / Sugai, K. / Horiuchi, T. et al. | 1996
- 375
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Hot-carriers at low voltages: new experimental evidences and open issuesSelmi, L. / Ghetti, A. / Bez, R. et al. | 1996
- 375
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Hot-Carriers at Low Voltages: New Experimental Evidences and Open Issues (Invited Paper)Selmi, L. / Fischer, B. / Ghetti, A. / Bez, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 379
-
Monte Carlo simulation of low voltage hot carrier effects in non volatile memory cellsGhetti, A. / Selmi, L. / Bez, R. / Sangiorgi, E. et al. | 1996
- 383
-
Is there experimental evidence for a difference between surface and bulk impact ionization in silicon?Jungemann, C. / Yamaguchi, S. / Goto, H. et al. | 1996
- 387
-
Scattering theory of the short channel MOSFETLundstrom, M. et al. | 1996
- 391
-
Understanding the differences in the effective-field dependence of electron and hole inversion layer mobilitiesJallepalli, S. / Shih, W.-K. / Bude, J.D. / Pinto, M.R. / Maziar, C.M. / Tasch, A.F. et al. | 1996
- 395
-
Effective mobility in heavily doped n-MOSFETs: measurements and modelsVilla, S. / Lacaita, A.L. / Perron, L. / Bez, R. et al. | 1996
- 399
-
Investigation of quantum effects in highly-doped MOSFETs by means of a self-consistent 2D modelSpinelli, A. / Pacelli, A. et al. | 1996
- 405
-
Micromachined tunable vertical-cavity surface-emitting lasersSugihwo, F. / Massengale, A.R. / Harris, J.S. et al. | 1996
- 409
-
Extremely high-power operation of 650 nm-band AlGaInP visible lasers with low optical absorption mirrorsFukuhisa, T. / Kidoguchi, I. / Adachi, H. / Tanaka, K. / Mannoh, M. / Takamori, A. et al. | 1996
- 413
-
First fabrication of AlGaAs/GaAs laser diodes with GaAs islands active regions on Si grown by droplet epitaxyEgawa, T. / Ogawa, A. / Jimbo, T. / Umeno, M. et al. | 1996
- 417
-
A novel electroluminescent diode with nanocrystalline silicon quantum dotsYoshida, T. / Yamada, Y. / Orii, T. et al. | 1996
- 421
-
Dynamic properties of InAs self-assembled quantum dots for spectral hole burning memory applicationHoriguchi, N. / Futatsugi, T. / Nakata, Y. / Yokoyama, N. et al. | 1996
- 425
-
RTD/HFET low standby power SRAM gain cellSeabaugh, A. / Beam, E. et al. | 1996
- 429
-
Experimental observation of Coulomb staircase in asymmetric tunnel barrier systemMatsumoto, Y. / Hanajiri, T. / Toyabe, T. / Sugano, T. et al. | 1996
- 429
-
Experimental Observation of Coulomb Staircase in an Asymmetric Tunnel Barrier SystemMatsumoto, Y. / Hanajiri, T. / Toyabe, T. / Sugano, T. / Institute of Electrical and Electronics Engineers et al. | 1996
- 435
-
Novel shallow junction technology using decaborane (B/sub 10/H/sub 14/)Goto, K. / Matsuo, J. / Sugii, T. / Minakata, H. / Yamada, I. / Hisatsugu, T. et al. | 1996
- 435
-
Novel Shallow Junction Technology Using Decaborane (B~1~0H~1~4)Goto, K. / Matsuo, J. / Sugii, T. / Minakata, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 439
-
-Doped Source/Drain 0.1m n-MOSFETs with Extremely Shallow JunctionsMurakami, E. / Harada, K. / Hisamoto, D. / Kimura, S. I. / Institute of Electrical and Electronics Engineers et al. | 1996
- 439
-
/spl delta/-doped source/drain 0.1-/spl mu/m n-MOSFETs with extremely shallow junctionsMurakami, E. / Harada, K. / Hisamoto, D. / Kimura, S. et al. | 1996
- 443
-
A 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing in an NH/sub 3/ ambientSegawa, M. / Yabu, T. / Arai, M. / Moriwaki, M. / Umimoto, H. / Sekiguchi, M. / Kanda, A. et al. | 1996
- 443
-
A 0.182m Ti-Salicided p-MOSFET with Shallow Junctions Fabricated by Rapid Thermal Pocessing in an NH3 AmbientSegawa, M. / Yabu, T. / Arai, M. / Moriwaki, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 447
-
Highly reliable W/TiN/pn-poly-Si gate CMOS technology with simultaneous gate and source/drain doping processWakabayashi, H. / Andoh, T. / Sato, T. / Yoshida, T. / Miyamoto, T. / Mogami, T. / Kunio, T. et al. | 1996
- 451
-
A thermally stable Ti-W salicide for deep-submicron logic with embedded DRAMFujii, K. / Kikuta, K. / Inoue, K. / Mikagi, K. / Chikaki, S. / Kikkawa, T. et al. | 1996
- 455
-
A Novel 0.15m CMOS Technology Using W/WNx/Polysilicon Gate Electrode and Ti Silicided Source/Drain DiffusionsTakagi, M. / Miyashita, K. / Koyama, H. / Nakajima, K. / Institute of Electrical and Electronics Engineers et al. | 1996
- 455
-
A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusionsTakagi, M.T. / Miyashita, K. / Koyama, H. / Nakajima, K. / Miyano, K. / Akasaka, Y. / Hiura, Y. / Inaba, S. / Azuma, A. / Koike, H. et al. | 1996
- 459
-
Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOSKotaki, H. / Kakimoto, S. / Nakano, M. / Matsuoka, T. / Adachi, K. / Sugimoto, K. / Fukushima, T. / Sato, Y. et al. | 1996
- 465
-
Characteristics and applications of a 0.6 /spl mu/m bipolar-CMOS-DMOS technology combining VLSI non-volatile memoriesContiero, C. / Galbiati, P. / Palmieri, M. / Vecchi, L. et al. | 1996
- 465
-
Characteristics and Applications of 0.6m Bipolar-CMOS-DMOS Technology Combining VLSI Non-Volatile Memories (Invited Paper)Contiero, C. / Galbiati, P. / Palmieri, M. / Vecchi, L. / Institute of Electrical and Electronics Engineers et al. | 1996
- 469
-
Optimized 25V, 0.34m cm^2 Very-Thin-RESURF (VTR), Drain Extended IGFETs in a Compressed BiCMOS ProcessTsai, C. Y. / Arch, J. / Efland, T. / Erdeljac, J. / Institute of Electrical and Electronics Engineers et al. | 1996
- 469
-
Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS processChin-Yu Tsai, / Arch, J. / Efland, T. / Erdeljac, J. / Hutter, L. / Mitros, J. / Yang, J.-Y. / Yuan, H.-T. et al. | 1996
- 473
-
Fabrication of a 300V, High Current (300mA/Output) Smart-Power IC Using Gate-Controlled SCRs on Bonded SOI (BSOI) TechnologyGonzalez, F. / Shekhar, V. / Chan, C. K. / Choy, B. / Institute of Electrical and Electronics Engineers et al. | 1996
- 473
-
Fabrication of a 300 V, high current (300 mA/output), smart-power IC using gate-controlled SCRs on bonded (BSOI) technologyGonzalez, F. / Shekhar, V. / Chia-Kung Chan, / Choy, B. / Chen, N. et al. | 1996
- 477
-
New high voltage SOI device structure eliminating substrate bias effectsNakagawa, A. / Yamaguchi, Y. / Yasuhara, N. / Hirayama, K. / Funaki, H. et al. | 1996
- 481
-
Simulations and measurements of cross-talk phenomena in BiCMOS technology for hard disk drivesde Cremoux, G. / Dubois, E. / Bardy, S. / Lebailly, J. et al. | 1996
- 485
-
Extraction of channel doping profile in DMOS transistorsPieracci, A. / Lanzoni, M. / Galbiati, P. / Manzini, S. / Contiero, C. / Ricco, B. et al. | 1996
- 489
-
Physically based description of quasi-saturation region of vertical DMOS power transistorsKreuzer, C.H. / Krischke, N. / Nance, P. et al. | 1996
- 495
-
Ultrathin nitrogen-profile engineered gate dielectric filmsHattangady, S.V. / Kraft, R. / Grider, D.T. / Douglas, M.A. / Brown, G.A. / Tiner, P.A. / Kuehne, J.W. / Nicollian, P.E. / Pas, M.F. et al. | 1996
- 499
-
High performance 0.2 /spl mu/m CMOS with 25 /spl Aring/ gate oxide grown on nitrogen implanted Si substratesLiu, C.T. / Lloyd, E.J. / Yi Ma, / Du, M. / Opila, R.L. / Hillenius, S.F. et al. | 1996
- 499
-
High Performance 0.2m CMOS with 2.5 nm Gate Oxide Grown on Nitrogen Implanted Si SubstratesLiu, C. / Lloyd, E. / Ma, Y. / Du, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 503
-
Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) for Single Transistor Memory Using Poly-Si source/Drain and BaMgF~4 DielectricLyu, J. S. / Kim, K. H. / Cha, J. Y. / Kim, B. W. / Institute of Electrical and Electronics Engineers et al. | 1996
- 503
-
Metal-ferroelectric-semiconductor field-effect transistor (MPSFET) for single transistor memory by using Poly-Si source/drain and BaMgF/sub 4/ dielectricJong-Son Lyu, / Be-Woo Kim, / Kwang-Ho Kim, / Ju-Youn Cha, / Hyung Joun Yoo, et al. | 1996
- 507
-
Trench storage node technology for gigabit DRAM generationsMuller, K.P. / Flietner, B. / Hwang, C.L. / Kleinhenz, R.L. / Nakao, T. / Ranade, R. / Tsunashima, Y. / Mii, T. et al. | 1996
- 511
-
Impact of an In-Situ Nitrogen and Phosphorus Co-Doped Amorphous Silicon as the Scalable and Reliable Floating Gate of Flash MemoryKaneoka, T. / Anma, M. / Itoh, H. / Hirayama, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 515
-
Ultra fast write speed, long refresh time, low power F-N operated volatile memory cell with stacked nanocrystalline Si filmShih-Jye Shen, / Chrong-Jung Lin, / Ching-Hsiang Hsu, C. et al. | 1996
- 521
-
IC MEMS microtransducersBaltes, H. / Paul, O. / Korvink, J.G. / Schneider, M. / Buhler, J. / Schneeberger, N. / Jaeggi, D. / Malcovati, P. / Hornung, M. / von Arx, M. et al. | 1996
- 521
-
IC MEMs Microtransducers (Invited Paper)Baltes, H. / Paul, O. / Korvink, J. / Schneider, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 525
-
(6H)-Si Pressure Sensors at 350 COkojie, R. / Ned, A. / Kurtz, A. / Carr, W. N. / Institute of Electrical and Electronics Engineers et al. | 1996
- 525
-
/spl alpha/(6H)-SiC pressure sensors at 350/spl deg/COkojie, R.S. / Ned, A.A. / Kurtz, A.D. / Carr, W.N. et al. | 1996
- 529
-
A low-voltage force-balanced barometric pressure sensorGogoi, B.P. / Mastrangelo, C.H. et al. | 1996
- 533
-
Temperature calibration of CMOS magnetic vector probe for contactless angle measurement systemSchneider, M. / Haberli, A. / Metz, M. / Malcovati, P. / Baltes, H. et al. | 1996
- 537
-
Offset reduction in multicollector magnetotransistorsMetz, M. / Schneider, M. / Haberli, A. / Baltes, H. et al. | 1996
- 541
-
Cylindrical Hall deviceBlanchard, H. / Chiesi, L. / Racz, R. / Popovic, R.S. et al. | 1996
- 545
-
Smart force sensors for scanning force microscope using the micromachined piezoelectric PZT cantileversChengkuo Lee, / Itoh, T. / Maeda, R. / Suga, T. et al. | 1996
- 549
-
An ultrasensitive uncooled heat-balancing infrared detectorLiu, C.C. / Mastrangelo, C.H. et al. | 1996
- 555
-
CMOS technology scaling, 0.1 /spl mu/m and beyondDavari, B. et al. | 1996
- 555
-
CMOS Technology Scaling 0.1m and Beyond (Invited Paper)Davari, B. / Institute of Electrical and Electronics Engineers et al. | 1996
- 559
-
Search for the optimal channel architecture for 0.18/0.12 /spl mu/m bulk CMOS experimental studyBouillon, P. / Skotnicki, T. / Kelaidis, C. / Gwoziecki, R. / Dollfus, P. / Regolini, J.-L. / Sagnes, I. / Bodnar, S. et al. | 1996
- 559
-
Search for the Optimal Channel Architecture for 0.18/0.12 m Bulk CMOS-Experimental StudyBouillon, P. / Skotnicki, T. / Kelaidis, C. / Gwoziecki, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 563
-
A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)Hong, Q.Z. / Nandakumar, M. / Aur, S. / Hu, J.C. / Chen, I.-C. et al. | 1996
- 563
-
A Sub-0.18m Gate Length CMOS Technology for High Performance (1.5V) and Low Power (1.0V)Rodder, M. / Hong, Q. Z. / Nandakumar, M. / Aur, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 567
-
Degradation of MOSFETs drive current due to halo ion implantationHyunsang Hwang, / Dong-Hoon Lee, / Jeong Mo Hwang, et al. | 1996
- 567
-
Degradation of MOSFETs Drive Currant Due to Halo Ion ImplantationHwang, H. / Lee, D.-H. / Hwang, J. / Institute of Electrical and Electronics Engineers et al. | 1996
- 571
-
Anomalous Short-Channel Effects in 0.1m MOSFETsCrabbe, E. / Logan, R. / Snare, J. / Agnello, P. / Institute of Electrical and Electronics Engineers et al. | 1996
- 571
-
Anomalous short-channel effects in 0.1 /spl mu/m MOSFETsLogan, R. / Snare, J. / Agnello, P. / Sun, J. et al. | 1996
- 575
-
High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicideHori, A. / Umimoto, H. / Nakaoka, H. / Sekiguchi, M. / Segawa, M. / Arai, M. / Takase, M. / Kanda, A. et al. | 1996
- 575
-
High Speed 0.1 m Dual Gate CMOS with Low Energy Phosphorus/Boron Implantation and Cobalt SalicideHori, A. / Umimoto, H. / Nakaoka, H. / Sekiguchi, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 579
-
Low resistive ultra shallow junction for sub 0.1 /spl mu/m MOSFETs formed by Sb implantationShibahara, K. / Mifuji, N. / Kawabata, K. / Kugimiya, T. / Furumoto, H. / Yokoyama, S. / Nagata, M. / Miyazaki, S. / Hirose, M. et al. | 1996
- 579
-
Low Resistive Ultra Shallow Junction for Sub 0.1m MOSFETs formed by Sb ImplantationShibahara, K. / Mifuji, M. / Kugimiya, T. / Furumoto, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 583
-
Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channelSayama, H. / Kuroi, T. / Shimizu, S. / Shirahata, M. / Okumura, Y. / Inuishi, M. / Miyoshi, H. et al. | 1996
- 589
-
A 0.23m^2 Double Self-Aligned Contact Cell for Gigabit DRAMs with a Ge-Added Vertical Epitaxial Si PadKoga, H. / Kasai, N. / Hada, H. / Tatsumi, T. / Institute of Electrical and Electronics Engineers et al. | 1996
- 589
-
A 0.23 /spl mu/m/sup 2/ double self-aligned contact cell for gigabit DRAMs with a Ge-added vertical epitaxial Si padKoga, H. / Kasai, N. / Hada, H. / Tatsumi, T. / Mori, H. / Iwao, S. / Saino, K. / Yamaguchi, H. / Nakajima, K. / Yamada, Y. et al. | 1996
- 593
-
Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyondLee, J.Y. / Kim, K.N. / Shin, Y.C. / Lee, K.H. / Kim, J.S. / Kim, D.H. / Park, J.W. / Lee, J.G. et al. | 1996
- 597
-
A new planar stacked technology (PST) for scaled and embedded DRAMsSim, S.P. / Lee, W.S. / Ohu, Y.S. / Choe, H.C. / Kim, J.H. / Ban, H.D. / Kim, I.C. / Chang, Y.H. / Lee, Y.J. / Kang, H.K. et al. | 1996
- 601
-
240 nm pitch 4 GDRAM array MOSFET technologies with X-ray lithographySunouchi, K. / Kawaguchiya, H. / Matsuda, S. / Nomura, H. / Shine, T. / Murooka, K. / Sugihara, S. / Mitsui, S. / Kondo, K. / Kikuchi, Y. et al. | 1996
- 605
-
Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)Il-Kwon Kim, / Woo-Tag Kang, / Joon-Hee Lee, / Sunil Yu, / Sang-Cheol Lee, / Kyehee Yeom, / Yun-Gi Kim, / Duck-Hyung Lee, / Giho Cha, / Byoung Hun Lee, et al. | 1996
- 609
-
16 Mb DRAM/SOI technologies for sub-1 V operationOashi, T. / Eimori, T. / Morishita, F. / Iwamatsu, T. / Yamaguchi, Y. / Okuda, F. / Shimomura, K. / Shimano, H. / Sakashita, N. / Arimoto, K. et al. | 1996
- 615
-
3D GIPER: global interconnect parameter extractor for full-chip global critical path analysisOh, S.Y. / Moll, J. / Nakagawa, O.S. / Rahmat, K. / Chang, N. / Hu, D. / Chow, J. / Young, T. / Ho, W. et al. | 1996
- 619
-
Interconnect Capacitance, Crosstalk, and Signal Delay for 0.35 m CMOS TechnologyCho, D. / Eo, Y. S. / Seung, M. / Kim, N. / Institute of Electrical and Electronics Engineers et al. | 1996
- 619
-
Interconnect capacitance, crosstalk, and signal delay for 0.35 /spl mu/m CMOS technologyCho, D.H. / Eo, Y.S. / Seung, M.H. / Kim, N.H. / Wee, J.K. / Kwon, O.K. / Park, H.S. et al. | 1996
- 623
-
Experimental results and modeling of noise coupling in a lightly doped substrateBlalack, T. / Lau, J. / Clement, F.J.R. / Wooley, B.A. et al. | 1996
- 627
-
The effect of statistical dopant fluctuations on MOS device performanceStolk, P.A. / Klaassen, D.B.M. et al. | 1996
- 631
-
A statistical critical dimension control at CMOS cell levelMisaka, A. / Goda, A. / Matsuoka, K. / Umimoto, H. / Odanaka, S. et al. | 1996
- 635
-
E-T based statistical modeling and compact statistical circuit simulation methodologiesChen, J.C. / Chenming Hu, / Wan, C.-P. / Bendix, P. / Kapoor, A. et al. | 1996
- 645
-
Integrated p-i-n/HBT Photoreceivers for Optical Communications (Invited Paper)Lunardi, L. / Chandrasekhar, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 645
-
Integrated p-i-n/HBT photoreceivers for optical communicationsLunardi, L.M. / Chandrasekhar, S. et al. | 1996
- 649
-
A novel technique to reduce crosstalk in monolithically integrated high speed photoreceiver arraysSyao, K.C. / Gutierrez-Aitken, A.L. / Yang, K. / Zhang, X. / Haddad, / Bhattacharya, P. et al. | 1996
- 653
-
Monolithic integrated MSM-2DEG PD/HEMT photoreceiver based on an identical InP/InGaAs heterostructureHorstmann, M. / Marso, H. / Kordos, P. et al. | 1996
- 657
-
Optoelectronic integrated receiver for inter-MCM and inter-chip optical interconnectsHeremans, P. / Ayadi, K. / Kuijk, M. / Bickel, G. / Vounckx, R. / Borghs, G. et al. | 1996
- 661
-
A vertical-cavity P-i-N SiGe/Si photodetector for Si-based OEICsMorikawa, T. / Sugiyama, M. / Tatsumi, T. / Sato, K. / Tashiro, T. et al. | 1996
- 665
-
Epitaxial SiGeC/Si Photodetector with Response in the 1.3-1.55m Wavelength RangeHuang, F. F. Y. / Thomas, S. G. / Chu, M. / Wang, K. L. / Institute of Electrical and Electronics Engineers et al. | 1996
- 665
-
Epitaxial SiGeC/Si photodetector with response in the 1.3-1.55 /spl mu/m wavelength rangeHuang, F.Y. / Thomas, S.G. / Chu, M. / Wang, K.L. / Theodore, N.D. et al. | 1996
- 669
-
Corrugated quantum well infrared photodetectorsChen, C.J. / Choi, K.K. / Tsui, D.C. et al. | 1996
- 675
-
A stacked capacitor with an MOCVD-(Ba,Sr)TiO/sub 3/ film and a RuO/sub 2//Ru storage node on a TiN-capped plug for 4 Gbit DRAMs and beyondYamaguchi, H. / Iizuka, T. / Koga, H. / Takemura, K. / Sone, S. / Yabuta, H. / Yamamichi, S. / Lesaicherre, P. / Suzuki, M. / Kojima, Y. et al. | 1996
- 675
-
A Stacked Capacitor with an MOCVD-(Ba,Sr)TiO~3 Film and a RuO~2/Ru Storage Node on a TiN-Capped Plug for 4 Gbit DRAMa and BeyondYamaguchi, H. / Iizuka, T. / Koga, H. / Takemura, K. / Institute of Electrical and Electronics Engineers et al. | 1996
- 679
-
Ir-electroded BST thin film capacitors for 1 giga-bit DRAM applicationTung-Sheng Chen, / Hadad, D. / Balu, V. / Jiang, B. / Shao-Hong Kuah, / McIntyre, P.C. / Summerfelt, S.R. / Anthony, J.M. / Lee, J.C. et al. | 1996
- 679
-
Ir-Electrode BST Thin Film Capacitors for 1 Giga-Bit DRAM ApplicationChen, T.-S. / Hadad, D. / Balu, V. / Jiang, B. / Institute of Electrical and Electronics Engineers et al. | 1996
- 683
-
Electrical Characterization of CVD TiN Upper Electrode for Ta~2O~5 CapacitorLee, M.-B. / Lee, H.-D. / Park, B.-L. / Chung, U.-I. / Institute of Electrical and Electronics Engineers et al. | 1996
- 683
-
Electrical characterization of CVD TiN upper electrode for Ta/sub 2/O/sub 5/ capacitorMyoung-Bum Lee, / Hyeon-Deok Lee, / Byung-Lyul Park, / U-In Chung, / Young-Bum Koh, / Moon-Yong Lee, et al. | 1996
- 687
-
A new post-deposition annealing method using furnace N/sub 2/O for the reduction of leakage current of CVD Ta/sub 2/O/sub 5/ storage capacitorsSun, S.C. / Chen, T.F. et al. | 1996
- 687
-
A New Post-Deposition Annealing Method Using Furnace N~2O for the Reduction of Leakage Current of CVD Ta~2O~5 Storage CapacitorsSun, S. / Chen, T. / Institute of Electrical and Electronics Engineers et al. | 1996
- 691
-
Crystalline-buffer-layer-aided (CBL) sputtering technique for mega-bit ferroelectric memory devices with SrBi/sub 2/Ta/sub 2/O/sub 9/ capacitorsMatsuki, T. / Hayashi, Y. / Kunio, T. et al. | 1996
- 691
-
Crystalline-Buffer Layer-Aided (CBL) Sputtering Technique for Mega-bit Ferroelectric Memory Devices with SrBi~2Ta~2O~9 CapacitorsMatsuki, T. / Hayashi, Y. / Kunio, T. / Institute of Electrical and Electronics Engineers et al. | 1996
- 695
-
Novel Ferroelectric Epitaxial (Ba,Sr)TiO~3 Capacitor for Deep Sub-Micron Memory ApplicationsKawakubo, T. / Abe, K. / Komatsu, S. / Sano, K. / Institute of Electrical and Electronics Engineers et al. | 1996
- 695
-
Novel ferroelectric epitaxial (Ba,Sr)TiO/sub 3/ capacitor for deep sub-micron memory applicationsKawakubo, T. / Abe, K. / Komatsu, S. / Sano, K. / Yanase, N. / Mochizuki, H. et al. | 1996
- 699
-
A Now High Temperature Electrode-Barrier Technology on High Density Ferroelectric Capacitor StructureOnishi, S. / Nagata, M. / Mitari, S. / Ito, Y. / Institute of Electrical and Electronics Engineers et al. | 1996
- 699
-
A new high temperature electrode-barrier technology on high density ferroelectric capacitor structureOnishi, S. / Nagata, M. / Mitarai, S. / Ito, Y. / Kudo, J. / Sakiyama, K. / Desu, S.B. / Bhatt, H.D. / Vijay, D.P. / Hwang, Y. et al. | 1996
- 705
-
3-dimensional simulation of thermal diffusion and oxidation processesSenez, V. / Bozek, S. / Baccus, B. et al. | 1996
- 709
-
The influence of oxidation-induced stress on the generation current and its impact on scaled device performanceSmeys, P. / Griffin, P.B. / Rek, Z.U. / De Wolf, I. / Saraswat, K.C. et al. | 1996
- 713
-
Monte Carlo Simulation of the Ion Implantation Damage Process in SiliconTian, S. / Morris, S. / Morris, M. / Obradovic, B. / Institute of Electrical and Electronics Engineers et al. | 1996
- 713
-
Monte Carlo simulation of ion implantation damage process in siliconTian, S. / Morris, S.J. / Morris, M. / Obradovic, B. / Tasch, A.F. et al. | 1996
- 717
-
An efficient method for modeling the effect of implant damage on NMOS devices using effective profiles and device simulationVasanth, K. / Saxena, S. / McNeil, V. / List, S. / Davis, J. / Kapila, D. et al. | 1996
- 721
-
Modeling of boron, phosphorus, and arsenic implants into single-crystal silicon over a wide energy range (few keV to several MeV)Morris, S.J. / Obradovic, B. / Yang, S.-H. / Tasch, A.F. et al. | 1996
- 727
-
Impacts of antenna layout enhanced charging damage on MOSFET reliability and performanceYamada, T. / Eriguchi, K. / Kosaka, Y. / Hatada, K. et al. | 1996
- 731
-
Inductively coupled plasma (ICP) metal etch damage to 35-60 A gate oxideKrishnan, S. / Dostalik, W.W. / Brennan, K. / Aur, S. / Rangan, S. / Ashok, S. et al. | 1996
- 731
-
Inductively Coupled Plasma (ICP) Metal Etch Damage to 35-60Gate OxideKrishnan, S. / Dostalik, B. / Brennan, K. / Aur, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 735
-
Effects of metal coverage on MOSFET matchingTuinhout, H. / Pelgrom, M. / Penning de Vries, R. / Vertregt, M. et al. | 1996
- 739
-
Impact of pattern density on plasma damage of CMOS LSIsMiyamoto, K. / Nakamura, J. / Hatanaka, K. / Hashimoto, T. / Tamura, I. / Maeda, T. / Sato, K. / Kakumu, M. et al. | 1996
- 743
-
Effect of mechanical stress on reliability of gate-oxide film in MOS transistorsMiura, H. / Ikeda, S. / Suzuki, N. et al. | 1996
- 747
-
Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)Tai-Su Park, / Yu Gyun Shin, / Han Sin Lee, / Moon Han Park, / Sang Dong Kwon, / Ho Kyu Kang, / Young Bum Koh, / Moon Yong Lee, et al. | 1996
- 751
-
Highly-reliable ultra thin gate oxide formation processIwamoto, T. / Morita, M. / Ohmi, T. et al. | 1996
- 755
-
Suppression of V/sub th/ fluctuation by minimizing transient enhanced diffusion for deep sub-quarter micron MOSFETOno, A. / Sakai, I. et al. | 1996
- 755
-
Suppression of Vth Fluctuation by Minimizing Transient Enhanced Diffusion for Deep Sub-Quarter Micron MOSFETOno, A. / Sakai, I. / Institute of Electrical and Electronics Engineers et al. | 1996
- 761
-
Fabrication of surface micromachined polysilicon actuators using dry release process of HF gas-phase etchingJong Hyun Lee, / Hoi Hwan Chung, / Seung Youl Kang, / Jong Tae Baek, / Hyung Joun Yoo, et al. | 1996
- 765
-
A high sensitivity z-axis torsional silicon accelerometerSelvakumar, A. / Ayazi, F. / Najafi, K. et al. | 1996
- 769
-
A novel structure of a piezoresistive accelerometer with lateral detection using precise fabrication techniquesShin-ogi, M. / Kato, K. / Mandai, M. / Saitoh, Y. et al. | 1996
- 773
-
High frequency microelectromechanical IF filtersBannon, F.D. / Clark, J.R. / Nguyen, C.T.-C. et al. | 1996
- 777
-
Thin Film Magnetostrictive Sensor with On-Chip Readout end attoFarad Capacitance ResolutionLu, Y. / Nathan, A. / Manku, T. / Ning, Y. / Institute of Electrical and Electronics Engineers et al. | 1996
- 777
-
Thin film magnetostrictive sensor with on-chip readout and attoFarad capacitance resolutionLu, Y. / Nathan, A. / Manku, T. / Ning, Y. et al. | 1996
- 781
-
New degradation phenomenon in wide channel poly-Si TFTs fabricated by low temperature processOhshima, H. et al. | 1996
- 785
-
LIQUID a complete simulation system for AMLCDsRollins, J.G. / Scrobohaci, P.G. / Durbeck, D. et al. | 1996
- 791
-
Modeling transient diffusion following high energy implantationRafferty, C.S. / Gossmann, H.-J. / Kamgar, A. / Jacobson, D.C. / Lloyd, E.J. / Hillenius, S.J. / Vuong, H.-H. / Becerro, J. / Vaidya, H.M. / Lytle, S.A. et al. | 1996
- 795
-
Dopant redistribution during gate oxidation including transient enhanced diffusion in oxidizing ambientUchida, T. / Eikyu, K. / Fujinaga, M. / Teramoto, A. / Miyoshi, H. et al. | 1996
- 799
-
Analytical models for transient diffusion and activation of ion-implanted boron during rapid thermal annealing considering ramp-up periodSuzuki, K. / Aoki, M. / Kataoka, Y. / Sasaki, N. / Hoefler, A. / Feudel, T. / Strecker, N. / Fichtner, W. et al. | 1996
- 803
-
Dopant diffusion model refinement and its impact on the calculation of reverse short channel effectHane, M. / Ikezawa, T. / Hiroi, M. / Matsumoto, H. et al. | 1996
- 807
-
Modeling C-V Shifts in Boron/BF2-Implanted CapacitorsVuong, H. H. / Rafferty, C. / Mansfield, W. / Luftman, H. / Institute of Electrical and Electronics Engineers et al. | 1996
- 807
-
Modeling C-V shifts in boron/BF/sub 2/-implanted capacitorsVuong, H.-H. / Rafferty, C.S. / Mansfield, W. / Luftman, H. / Jacobson, D. / Pinto, M.R. / Eshraghi, S.A. / McMacken, J.R. / Ham, T.E. et al. | 1996
- 811
-
Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETsVoorde, P.V. / Griffin, P.B. / Yu, Z. / Oh, S.-Y. / Dutton, R.W. et al. | 1996
- 815
-
Optimization of channel profiles for ultra-short MOSFETs by quantum simulationFiegna, C. / Abramo, A. et al. | 1996
- 821
-
The Impact of High Pressure Dry O~2 Oxidation on Sub-quarter Micron Planarized LOCOSYamashita, I. / Kuroi, T. / Uchida, T. / Komori, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 821
-
The impact of high pressure dry O/sub 2/ oxidation on sub-quarter micron planarized LOCOSYamashita, T. / Kuroi, T. / Uchida, T. / Komori, S. / Kobayashi, K. / Inuishi, M. / Miyoshi, H. et al. | 1996
- 825
-
Nitride cladded poly-Si spacer LOCOS (NCPSL) isolation technology for the 1 giga bit DRAMKim, S.E. / Kim, Y.D. / Ahn, D.H. / Hong, S.J. / Shin, Y.G. / Park, Y.W. / Kang, H.K. / Koh, Y.B. / Lee, M.Y. et al. | 1996
- 829
-
A Shallow Trench Isolation Using LOCOS Edge for Preventing Corner Effects for 0.25/0.18m CMOS Technologies and BeyondChatterjee, A. / Rogers, D. / McKee, J. / Ali, I. / Institute of Electrical and Electronics Engineers et al. | 1996
- 829
-
A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyondChatterjee, A. / Rogers, D. / McKee, J. / Ali, I. / Nag, S. / Chen, I.-C. et al. | 1996
- 833
-
Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memoriesWatanabe, H. / Shimizu, K. / Takeuchi, Y. / Aritome, S. et al. | 1996
- 833
-
Corner-Rounded Shallow Trench Isolation Technology to Reduce the Stress-Induced Tunnel Oxide Leakage Current for Highly Reliable Flesh MemoriesWatanabe, H. / Shimizu, K. / Takeuchi, Y. / Aritome, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 837
-
A novel 0.25 /spl mu/m shallow trench isolation technologyChen, C. / Chou, J.W. / Lur, W. / Sun, S.W. et al. | 1996
- 837
-
A Novel 0.25m Shallow Trench Isolation TechnologyChen, C. / Chou, J. W. / Lur, W. / Sun, S. W. / Institute of Electrical and Electronics Engineers et al. | 1996
- 841
-
Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologiesNag, S. / Chatterjee, A. / Taylor, K. / Ali, I. / O'Brien, S. / Aur, S. / Luttmer, J.D. / Chen, I.C. et al. | 1996
- 841
-
Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25m TechnologiesNag, S. / Chatterjee, A. / Taylor, K. / Ali, I. / Institute of Electrical and Electronics Engineers et al. | 1996
- 847
-
A high performance 0.25 /spl mu/m logic technology optimized for 1.8 V operationBohr, M. / Ahmed, S.S. / Ahmed, S.U. / Bost, M. / Ghani, T. / Greason, J. / Hainsey, R. / Jan, C. / Packan, P. / Sivakumar, S. et al. | 1996
- 847
-
A High Performance 0.25m Logic Technology Optimized for 1.8V OperationBohr, M. / Ahmed, S. S. / Ahmed, S. U. / Bost, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 851
-
0.18 m Dual Vt MOSFET Process and Energy-Delay MeasurementChen, Z. / Diaz, C. / Plummer, J. / Cao, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 851
-
0.18 um dual Vt MOSFET process and energy-delay measurementZhongjian Chen, / Diaz, C. / Plummer, J.D. / Min Cao, / Greene, W. et al. | 1996
- 855
-
The impact of the floating-body effect suppression on SOI integrated circuitsTerauchi, M. / Nishiyama, A. / Mizuno, T. / Yoshimi, M. / Watanabe, S. et al. | 1996
- 859
-
Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplaceAhlgren, D.C. / Gilbert, M. / Greenberg, D. / Jeng, J. / Malinowski, J. / Nguyen-Ngoc, D. / Schonenberg, K. / Stein, K. / Groves, R. / Walter, K. et al. | 1996
- 865
-
Determination of threshold energy for hot electron interface state generationBude, J.D. / Iizuka, T. / Kamakura, Y. et al. | 1996
- 869
-
Localized Charge Injection in the Gate Oxide Over Gate-Drain Overlap Region: Mechanism, Device Dependence, and Application for Device DiagnosticsBrozek, T. / Sridharan, A. / Werking, J. / Chan, Y. / Institute of Electrical and Electronics Engineers et al. | 1996
- 869
-
Localized charge injection through the gate oxide over gate-drain overlap region: mechanism, device dependence, and application for device diagnosticsBrozek, T. / Sridharan, A. / Werking, J. / Chan, Y.D. / Viswanathan, C.R. et al. | 1996
- 873
-
Competing AC hot-carrier degradation mechanisms in surface-channel p-MOSFETs during pass transistor operationBravaix, A. / Vuillaume, D. / Goguenheim, D. / Lassarre, V. / Haoad, M. et al. | 1996
- 877
-
Hot-carrier effects in deep submicron thin film SOI MOSFETsRenn, S.H. / Pelloie, J.L. / Balestra, F. et al. | 1996
- 881
-
Anomalous hot-carrier induced degradation in very narrow channel nMOSFETs with STI structureNishigohri, M. / Ishimaru, K. / Takahashi, M. / Unno, Y. / Okayama, Y. / Matsuoka, F. / Kinugawa, M. et al. | 1996
- 885
-
Hot carrier induced degradation of CMOS current mirrors and current sourcesThewes, R. / Goser, K.F. / Weber, W. et al. | 1996
- 889
-
Novel octagonal device structure for output transistors in deep-submicron low-voltage CMOS technologyMing-Dou Ker, / Tain-Shun Wu, et al. | 1996
- 893
-
Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /spl mu/m CMOS processAmerasekera, A. / McNeil, V. / Rodder, M. et al. | 1996
- 893
-
Correlating Drain Junction Scaling Salicide Thickness and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 m CMOS ProcessAmerasekera, A. / McNeil, V. / Rodder, M. / Institute of Electrical and Electronics Engineers et al. | 1996
- 899
-
CCD Imagers for Broadcast Applications (Invited Paper)Stoldt, H. / Theuwissen, A. / Vledder, E. / Centen, P. / Institute of Electrical and Electronics Engineers et al. | 1996
- 899
-
CCD imagers for broadcast applicationsStoldt, H. / Theuwissen, A.J.P. / Vledder, F.F. / Centen, P.G.M. / Mierop, A. / Kleimann, A.C.M. / Peek, H.L. / Verbugt, D.W.E. / Hartog, P.B. / de Gruyter, R.H.S. et al. | 1996
- 903
-
A two-phase CCD register with charge injected floating gate electrodesHatano, K. / Yamada, T. / Nakashiba, Y. / Furumiya, M. / Morimoto, M. / Nakano, T. / Kawakami, Y. / Taniji, Y. / Mutoh, N. / Orihara, K. et al. | 1996
- 907
-
An FT-CCD Imager with True 2.4 x 2.4 m^2 Pixels in Double Membrane Poly-Si TechnologyPeek, H. / Verbugt, D. / Beenhakkers, M. / Huinink, S. / Institute of Electrical and Electronics Engineers et al. | 1996
- 907
-
An FT-CCD imager with true 2.4/spl times/2.4 /spl mu/m/sup 2/ pixels in double membrane poly-Si technologyPeek, H.L. / Verbugt, D.W. / Beenhakkers, M.J. / Huinink, W.F. / Kleimann, K.C. et al. | 1996
- 911
-
A 200 x 200 CCD Image Sensor Fabricated on High-Resistivity SiliconHolland, S. / Goldhaber, G. / Groom, D. / Moses, W. / Institute of Electrical and Electronics Engineers et al. | 1996
- 911
-
A 200/spl times/200 CCD image sensor fabricated on high-resistivity siliconHolland, S.E. / Goldhaber, G. / Groom, D.E. / Moses, W.W. / Pennypacker, C.R. / Perlmutter, S. / Wang, N.W. / Stover, R.J. / Wei, M. et al. | 1996
- 915
-
CMOS Active Pixel Image Sensors Fabricated Using a 1.8V, 0.25 m CMOS TechnologyWong, H.-S. / Chang, R. / Crabbe, E. / Agnello, P. / Institute of Electrical and Electronics Engineers et al. | 1996
- 915
-
CMOS active pixel image sensors fabricated using a 1.8 V, 0.25 /spl mu/m CMOS technologyChang, R.T. / Crabbe, E. / Agnello, P. et al. | 1996
- 919
-
High dynamic range, low-noise floating-gate photosensorKub, F.J. / Lin, H.C. et al. | 1996
- 923
-
A CMOS image sensor with combined analog nonvolatile storage capabilityAslam, A. / Brockherde, W. / Hosticka, B.J. / Vogt, H. / Zimmer, G. et al. | 1996
- 931
-
First Demonstration of p-HEMTs in the newly developed GaAs On Insulator (GOI) TechnologyParikh, P. / Chavarkar, P. / Wu, Y.F. / Pinsukanjana, P. / Mishra, U.K. et al. | 1996
- 931
-
20 GHz Power PHEMTs with Power-Added Efficiency of 68% at 2 VoltsKao, M. Y. / Saunier, P. / Ketterson, A. / Yarborough, R. / Institute of Electrical and Electronics Engineers et al. | 1996
- 934
-
Full chip optical imaging of logic state evolution in CMOS circuitsKash, J.A. / Tsang, J.C. et al. | 1996
- 937
-
A sixteen level scheme enabling 64 Mbit flash memory using 16 Mbit technologyKencke, D.L. / Richart, R. / Garg, S. / Banerjee, S.K. et al. | 1996
- 940
-
Submm-wave monolithic RTD oscillator arrays to 650 GHzMolnar, A.C. / Reddy, M. / Mondry, M.J. / Rodwell, M.J.W. / Allen, S.J. / Martin, S.C. / Muller, R.E. / Smith, R.P. et al. | 1996
- 943
-
Enhancement-mode p-channel GaAs MOSFETs on semi-insulating substratesRen, F. / Hong, M.W. / Hobson, W.S. / Kuo, J.M. / Lothian, J.R. / Mannaerts, J.P. / Kwo, J. / Chen, Y.K. / Cho, A.Y. et al. | 1996
- 946
-
Novel high aspect ratio aluminum plug for logic/DRAM LSIs using polysilicon-aluminum substitute (PAS)Horie, H. / Imai, M. / Itoh, A. / Arimoto, Y. et al. | 1996
- 949
-
A novel high-speed quasi-SOI power MOSFET with suppressed parasitic bipolar effect fabricated by reversed silicon wafer direct bondingMatsumoto, S. / Yachi, T. / Horie, H. / Arimoto, Y. et al. | 1996
- 952
-
Room temperature operation of Si single-electron memory with self-aligned floating dot gateNakajima, A. / Futatsugi, T. / Kosemura, K. / Fukano, T. / Yokoyama, N. et al. | 1996
- 955
-
Si single-electron MOS memory with nanoscale floating-gate and narrow channelLangjie Guo, / Leobandung, E. / Chou, S.Y. et al. | 1996
- 957
-
Integration of organic LEDs and amorphous Si TFTs onto unbreakable metal foil substratesWu, C.C. / Theiss, S. / Lu, M.H. / Sturm, J.C. / Wagner, S. et al. | 1996