X-masking during logic BIST and its impact on defect coverage (English)
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- New search for: Polian, I.
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- New search for: Hapke, F.
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- New search for: Wunderlich, H.-J.
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In:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
;
14
, 2
;
193-202
;
2006
- Article (Journal) / Electronic Resource
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Title:X-masking during logic BIST and its impact on defect coverage
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Contributors:Yuyi Tang, ( author ) / Wunderlich, H.-J. ( author ) / Piet Engelke, ( author ) / Polian, I. ( author ) / Becker, B. ( author ) / Schloffel, J. ( author ) / Hapke, F. ( author ) / Wittke, M. ( author )
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Published in:IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; 14, 2 ; 193-202
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Publisher:
- New search for: IEEE
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Publication date:2006-02-01
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Size:880349 byte
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents – Volume 14, Issue 2
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 97
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VLSI Architecture - An Asynchronous Architecture for Modeling Intersegmental Neural CommunicationPatel, G.N. et al. | 2006
- 97
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An asynchronous architecture for modeling intersegmental neural communicationPatel, G.N. / Reid, M.S. / Schimmel, D.E. / DeWeerth, S.P. et al. | 2006
- 111
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A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithmHernandez, O.J. et al. | 2006
- 111
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VLSI Architecture - A High-Performance VLSI Architecture for the Histogram Peak-Climbing Data Clustering AlgorithmHernandez, O.J. et al. | 2006
- 122
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Energy optimization of pipelined digital systems using circuit sizing and supply scalingDao, H.Q. / Zeydel, B.R. / Oklobdzija, V.G. et al. | 2006
- 122
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Energy Optimization and Management - Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply ScalingDao, H.Q. et al. | 2006
- 135
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Energy Optimization and Management - Energy Management for Battery-Powered Reconfigurable Computing PlatformsKhan, J. et al. | 2006
- 135
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Energy management for battery-powered reconfigurable computing platformsKhan, J. / Vemuri, R. et al. | 2006
- 148
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Low-power network-on-chip for high-performance SoC designKangmin Lee, / Se-Joong Lee, / Hoi-Jun Yoo, et al. | 2006
- 148
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Low Power - Low-Power Network-on-Chip for High-Performance SoC DesignLee, K. et al. | 2006
- 161
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Low Power - Low-Power Repeaters Driving RC and RLC Interconnects With Delay and Bandwidth ConstraintsChen, G. et al. | 2006
- 161
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Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraintsGuoqing Chen, / Friedman, E.G. et al. | 2006
- 173
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Low Power - A Combined Gate Replacement and Input Vector Control Approach for Leakage Current ReductionYuan, L. et al. | 2006
- 173
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A combined gate replacement and input vector control approach for leakage current reductionLin Yuan, / Gang Qu, et al. | 2006
- 183
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Design and Test - A Novel High-Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50-nm Double-Gate MOSFETMukhopadhyay, S. et al. | 2006
- 183
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A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFETMukhopadhyay, S. / Mahmoodi, H. / Roy, K. et al. | 2006
- 193
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Design and Test - X-Masking During Logic BIST and Its Impact on Defect CoverageTang, Y. et al. | 2006
- 193
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X-masking during logic BIST and its impact on defect coverageYuyi Tang, / Wunderlich, H.-J. / Piet Engelke, / Polian, I. / Becker, B. / Schloffel, J. / Hapke, F. / Wittke, M. et al. | 2006
- 203
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Layout-driven architecture synthesis for high-speed digital filtersDongku Kang, / Choo, H. / Muhammad, K. / Roy, K. et al. | 2006
- 203
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TRANSACTIONS BRIEFS - Layout-Driven Architecture Synthesis for High-Speed Digital FiltersKang, D. et al. | 2006
- 207
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A low-power correlation-derivative CMOS VLSI circuit for bearing estimationJulian, P. / Andreou, A.G. / Goldberg, D.H. et al. | 2006
- 207
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TRANSACTIONS BRIEFS - A Low-Power Correlation-Derivative CMOS VLSI Circuit for Bearing EstimationJulián, P. et al. | 2006
- 212
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Comments on "Carry checking/parity prediction adders and ALUs"Rodriguez-Navarro, J.J. et al. | 2006
- 212
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TRANSACTIONS BRIEFS - Comments on "Carry Checking-Parity Prediction Adders and ALUs"Rodriguez-Navarro, J.J. et al. | 2006
- 214
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CALLS FOR PAPERS - Call for Participation -- ISCAS'06| 2006
- 214
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2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)| 2006
- 215
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Order Form for Reprints| 2006
- 216
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Explore IEL IEEE's most comprehensive resource| 2006
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Table of contents| 2006
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2006