From VHDL register transfer level to SystemC transaction level modeling: a comparative case study (English)
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In:
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.
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355-360
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2003
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ISBN:
- Conference paper / Electronic Resource
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Title:From VHDL register transfer level to SystemC transaction level modeling: a comparative case study
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Contributors:Calazans, N. ( author ) / Moreno, E. ( author ) / Hessel, F. ( author ) / Rosa, V. ( author ) / Moraes, F. ( author ) / Carara, E. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2003-01-01
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Size:280944 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
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SystemC: from language to applications, from tools to methodologiesMartin, G. et al. | 2003
- 4
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System-level design for FPGAsLysaght, P. et al. | 2003
- 5
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High-performance RF/microwave integrated circuits in advanced logic CMOS technology: the coming of age for RF/digital mixed-signal system-on-a-packageFranca-Neto, L.M. et al. | 2003
- 9
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Design of a Low Noise Amplifier for CDMA Transceivers at 900 MHz in CMOS 0.35 mumAzevedo, J. A. P. / Pimenta, T. C. / IEEE et al. | 2003
- 9
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Design of a low noise amplifier for CDMA transceivers at 900 MHz in CMOS 0.35 /spl mu/mAzevedo, J.A.P. / Pimenta, T.C. et al. | 2003
- 14
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A methodology for CMOS low noise amplifier designRoa, E. / Soares, J.N. / Van Noije, W. et al. | 2003
- 20
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Design of a reusable rail-to-rail operational amplifierAguirre, P. / Silveira, F. et al. | 2003
- 26
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Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETsGimenez, S.P. / Pavanello, M.A. / Martino, J.A. / Adriaensen, S. / Flandre, D. et al. | 2003
- 35
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Boolean technology mapping based on logic decompositionDamiani, M. / Selchenko, A.Y. et al. | 2003
- 41
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Retiming finite state machines to control hardened data-pathsAuge, I. / Donnet, F. / Petrot, F. et al. | 2003
- 47
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Combining retiming and recycling to optimize the performance of synchronous circuitsCarloni, L.P. / Sangiovanni-Vincentelli, A.L. et al. | 2003
- 53
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Simplification of Toffoli networks via templatesMaslov, D. / Dueck, G.W. / Miller, D.M. et al. | 2003
- 61
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SystemC and the future of design languages: opportunities for users and researchMartin, G. et al. | 2003
- 65
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A new pipelined array architecture for signed multiplicationCosta, E. / Bampi, S. / Monteiro, J. et al. | 2003
- 71
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Novel design methodology for high-performance XOR-XNOR circuit designGoel, S. / Elgamel, M.A. / Bayoumi, M.A. et al. | 2003
- 79
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Towards a high-level synthesis of reconfigurable bit-serial architecturesRettberg, A. / Dittmann, F. / Zanella, M. / Lehmann, T. et al. | 2003
- 85
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DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software ArchitecturesVestias, M. P. / Neto, H. C. / IEEE et al. | 2003
- 85
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DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]Vestias, M.P. / Neto, H.C. et al. | 2003
- 93
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ME64-A Highly Scalable Hardware Parallel Architecture for Motion Estimation in FPGAZandonai, D. / Bampi, S. / Bergerman, M. / IEEE et al. | 2003
- 93
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ME64 - a highly scalable hardware parallel architecture motion estimation in FPGAZandonai, D. / Bampi, S. / Bergerman, M. et al. | 2003
- 99
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Hyperspectral images clustering on reconfigurable hardware using the k-means algorithmFilho, A.Gda.S. / Frery, A.C. / de Araujo, C.C. / Alice, H. / Cerqueira, J. / Loureiro, J.A. / de Lima, M.E. / Oliveira, Mdas.G.S. / Horta, M.M. et al. | 2003
- 105
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Design and prototyping of direct torque control of induction motors in FPGAsFerreira, S. / Haffner, F. / Pereira, L.F. / Moraes, F. et al. | 2003
- 111
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FPGA-based hardware architecture for neural networks: binary radix vs. stochasticNedjah, N. / Mourelle, Lde.M. et al. | 2003
- 119
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An XML format based integration infrastructure for IP based designVisarius, M. / Lessmann, J. / Hardt, W. / Kelso, F. / Thronicke, W. et al. | 2003
- 125
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Tangram - virtual integration of heterogeneous IP components in a distributed co-simulation environmentSouza, U.R.F. / Sperb, J.K. / de Mello, B.A. / Wagner, F.R. et al. | 2003
- 131
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A fast IP-core integration methodology for SoC designFilho, J.Ad.'O. / de Lima, M.E. / Maciel, P.R. / Moura, J. / Celso, B. et al. | 2003
- 137
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A universal high-performance analog interface for signal processing SOCsFabris, E.E. / Carro, L. / Bampi, S. et al. | 2003
- 145
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Architecture and implementation of multi-processor SoCs for advanced set-top box and digital TV systemsDutta, S. et al. | 2003
- 149
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Automatic generation of 1-of-M QDI asynchronous addersFragoso, J. / Sicard, G. / Renaudin, M. et al. | 2003
- 155
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Exclusion Relation of k Out of n and the Synthesis of Speed-Independent CircuitsPereira, A. / Borges, A. R. / Ferrari, A. / IEEE et al. | 2003
- 155
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Exclusion relation of k out of n and the synthesis of speed-independent circuits [asynchronous circuits]Pereira, A. / Borges, A.R. / Ferrari, A. et al. | 2003
- 163
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Algorithms and tools for network on chip based system designTang Lei, / Kumar, S. et al. | 2003
- 169
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SoCIN: a parametric and scalable network-on-chipZeferino, C.A. / Susin, A.A. et al. | 2003
- 177
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A low ripple fully integrated charge pump regulatorSoldera, J. / Vilas Boas, A. / Olmos, A. et al. | 2003
- 181
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A temperature compensated fully trimmable on-chip IC oscillatorOlmos, A. et al. | 2003
- 187
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Bias dependence of noise correlation in MAGFETsCastaldo, F.C. / Cajueiro, J.P.C. / dos Reis, C.A. et al. | 2003
- 191
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A charge correction cell for FGMOS-based circuitsRodriguez-Villegas, E.O. / Yufera, A. / Rueda, A. et al. | 2003
- 199
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Unified Theory to Build Cell-Level Transistor Networks from BDDsPoli, R. E. B. / Schneider, F. R. / Ribas, R. P. / Reis, A. I. / IEEE et al. | 2003
- 199
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Unified theory to build cell-level transistor networks from BDDs [logic synthesis]Poli, R.E.B. / Schneider, F.R. / Ribas, R.P. / Reis, A.I. et al. | 2003
- 205
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Modeling a reconfigurable system for computing the FFT in place via rewriting-logicAyala-Rincon, M. / Nogueira, R.B. / Llanos, C.H. / Jacobi, R.P. / Hartenstein, R.W. et al. | 2003
- 211
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Runtime analysis of synchronous programs for low-level real-time verificationLogothetis, G. / Schneider, K. / Metzler, C. et al. | 2003
- 217
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A consumer report on BDD packagesJanssen, G. et al. | 2003
- 225
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A new hybrid parallel/reconfigurable architecture: the X4CP32Azevedo, A. / Soares, R. / Silva, I.S. et al. | 2003
- 231
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Control development for mechatronic systems with a fully reconfigurable pipeline architectureRettberg, A. / Zanella, M. / Lehmann, T. / Dierkes, U. / Rustemeier, C. et al. | 2003
- 237
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Efficient processor instruction set extension by asynchronous reconfigurable datapath integrationBecker, J. / Thomas, A. / Scheer, M. et al. | 2003
- 243
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Situated learning on FPGA for superscalar microprocessor design educationTakahashi, R. / Ohiwa, H. et al. | 2003
- 251
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On-chip decoupling capacitor optimization for noise and leakage reductionChen, H.H. / Neely, J.S. / Wang, M.F. / Co, G. et al. | 2003
- 256
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Minimum-area shield insertion for explicit inductive noise reductionElgamel, M.A. / Bayoumi, M.A. et al. | 2003
- 261
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A new continuous switching window computation with crosstalk noiseWang, J.M. / Pinhong Chen, / Hafiz, O. et al. | 2003
- 267
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Improving simulated annealing placement by applying random and greedy mixed perturbations [IC layout]Hentschke, R.F. / Reis, R.A.D.L. et al. | 2003
- 267
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Improving Simulated Annealing Placement by Applying Random and Greedy Mixed PerturbationsHentschke, R. F. / da LReis, R. A. / IEEE et al. | 2003
- 275
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Future design tools for platform FPGAsLysaght, P. et al. | 2003
- 283
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Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitationsBecker, J. / Huebner, M. / Ullmann, M. et al. | 2003
- 289
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Dynamic reconfiguration behavior using generic FPGAs and FPIDsZuim, R.L. / Junior, C.J.N.C. / Moreira, L.F.E. / Fernandes, A.O. / da Mata, J.M. / da Silva, D.C. et al. | 2003
- 297
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Improving critical path identification in functional timing analysisFerrao, D. / Wilke, G. / Reis, R. / Guntzel, J.L. et al. | 2003
- 303
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A transistor sizing method applied to an automatic layout generation toolSantos, C. / Wilke, G. / Lazzari, C. / Reis, R. / Guntzel, J.L. et al. | 2003
- 311
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Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35mum TechnologyGirardi, A. / Cortes, F. P. / Fabris, E. / Bampi, S. / IEEE et al. | 2003
- 311
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Analog IC modules design using trapezoidal association of MOS transistors in 0.35 /spl mu/m technologyGirardi, A. / Cortes, F.P. / Fabris, E. / Bampi, S. et al. | 2003
- 317
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Digital background calibration technique for pipeline ADCs with multi-bit stagesGines, A.J. / Peralias, E.J. / Rueda, A. et al. | 2003
- 323
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Design methodologies for high-speed CMOS photoreceiver front-endsTissafi-Drissi, F. / O'Connor, I. / Mieyeville, F. / Gaffiot, F. et al. | 2003
- 329
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Testing RF signal paths using spectral analysis and subsampling [mixer example]Negreiros, M. / Schuler, E. / Carro, L. / Susin, A.A. et al. | 2003
- 329
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Testing RF Signal Paths Using Spectral Analysis and SubsamplingNegreiros, M. / Schuler, E. / Carro, L. / Susin, A. A. / IEEE et al. | 2003
- 337
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Accurate dependability analysis of CAN-based networked systemsPerez, J. / Sonza Reorda, M. / Violante, M. et al. | 2003
- 343
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ReCoNet: modeling and implementation of fault tolerant distributed reconfigurable hardwareHaubelt, C. / Koch, D. / Teich, J. et al. | 2003
- 343
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ReCoNet: Modeling and Implemention of Fault-Tolerant Distributed Reconfigurable HardwareHaubelt, C. / Koch, D. / Teich, J. / IEEE et al. | 2003
- 349
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CACO-PS: a general purpose cycle-accurate configurable power simulatorBeck, A.C.S. / Mattos, J.C.B. / Wagner, F.R. / Carro, L. et al. | 2003
- 355
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From VHDL register transfer level to SystemC transaction level modeling: a comparative case studyCalazans, N. / Moreno, E. / Hessel, F. / Rosa, V. / Moraes, F. / Carara, E. et al. | 2003
- 361
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Author index| 2003
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Proceedings 16th Symposium on Integrated Circuits and Systems Design. SBCCI 2003| 2003