A resiliency-aware scheduling approach for FPGA configuration: Preliminary results (English)
- New search for: Abramson, Jeremy
- New search for: Diniz, Pedro C.
- New search for: Abramson, Jeremy
- New search for: Diniz, Pedro C.
In:
22nd International Conference on Field Programmable Logic and Applications (FPL)
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471-472
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2012
- Conference paper / Electronic Resource
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Title:A resiliency-aware scheduling approach for FPGA configuration: Preliminary results
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Contributors:Abramson, Jeremy ( author ) / Diniz, Pedro C. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2012-08-01
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Size:330599 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Committee| 2012
- 1
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[Copyright notice]| 2012
- 1
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Technical program| 2012
- 1
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Dataflow supercomputingFlynn, Michael J. et al. | 2012
- 1
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Welcome to FPL2012Torresen, Jim / Koch, Dirk / Singh, Satnam et al. | 2012
- 1
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[Title page]| 2012
- 5
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Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filteringChen, Doris / Singh, Deshanand et al. | 2012
- 9
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Academic and industrial workshops| 2012
- 11
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Industrial sessions| 2012
- 14
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Detecting power attacks on reconfigurable hardwareMasle, Adrien Le / Luk, Wayne et al. | 2012
- 20
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Efficient and side-channel-secure block cipher implementation with custom instructions on FPGAMane, Suvarna / Taha, Mostafa / Schaumont, Patrick et al. | 2012
- 26
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CRUSH: Cognitive Radio Universal Software HardwareEichinger, George / Chowdhury, Kaushik / Leeser, Miriam et al. | 2012
- 33
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Data coding functions for Software Defined Radios implemented on R3TOSTorrego, Raul / Val, Inaki / Muxika, Enaut / Muxika, Eñaut / Iturbe, Xabier / Benkrid, Khaled et al. | 2012
- 41
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EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chipRavishankar, Chirag / Ananthanarayan, Sundaram / Garg, Siddharth / Kennings, Andrew et al. | 2012
- 49
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Limitations of incremental signal-tracing for FPGA debugHung, Eddie / Wilton, Steven J. E. et al. | 2012
- 57
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SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfigurationDevic, Florian / Torres, Lionel / Crenne, Jeremie / Badrignans, Benoit / Benoit, Pascal et al. | 2012
- 63
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FPGAs for trusted cloud computingEguro, Ken / Venkatesan, Ramarathnam et al. | 2012
- 71
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Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAsIngemarsson, Carl / Kallstrom, Petter / Gustafsson, Oscar et al. | 2012
- 75
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Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resourcesFeilen, Michael / Ihmig, Matthias / Schwarzbauer, Christian / Stechele, Walter et al. | 2012
- 83
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On the difficulty of pin-to-wire routing in FPGAsShah, Niyati / Rose, Jonathan et al. | 2012
- 91
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Routing algorithms for FPGAS with sparse intra-cluster routing crossbarsMohammed Moctar, Yehdhih Ould / Lemieux, Guy G. F. / Brisk, Philip et al. | 2012
- 99
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Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case studyBetkaoui, Brahim / Wang, Yu / Thomas, David B. / Luk, Wayne et al. | 2012
- 105
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Bio-inspired walking: A FPGA multicore system for a legged robotHenrey, Michael / Edmond, Sean / Shannon, Lesley / Menon, Carlo et al. | 2012
- 112
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A scalable FPGA-based design for field programmable large-scale ion channel simulationsCoapes, Graeme / Mak, Terrence / Luo, Jun Wen / Yakovlev, Alex / Poon, Chi-Sang et al. | 2012
- 120
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Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computationKono, Yoshiaki / Sano, Kentaro / Yamamoto, Satoru et al. | 2012
- 128
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FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometryNagy, Zoltan / Nemes, Csaba / Hiba, Antal / Kiss, Andras / Csik, Arpad / Szolgay, Peter et al. | 2012
- 136
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Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamicsAkamine, Takayuki / Inakagata, Kenta / Osana, Yasunori / Fujita, Naoyuki / Amano, Hideharu et al. | 2012
- 143
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Analytical placement for heterogeneous FPGAsGort, Marcel / Anderson, Jason H. et al. | 2012
- 151
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Profiling FPGA floor-planning effects on timing closureLamprecht, Jaren / Hutchings, Brad et al. | 2012
- 157
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Multi-kernel floorplanning for enhanced CGRASWood, Aaron / Knight, Adam / Ylvisaker, Benjamin / Hauck, Scott et al. | 2012
- 165
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Optimising explicit finite difference option pricing for dynamic constant reconfigurationJin, Qiwei / Becker, Tobias / Luk, Wayne / Thomas, David et al. | 2012
- 173
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Exploiting run-time reconfiguration in stencil computationNiu, Xinyu / Jin, Qiwei / Luk, Wayne / Liu, Qiang / Pell, Oliver et al. | 2012
- 181
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A two step hardware design method using CλaSHWester, Rinse / Baaij, Christiaan / Kuper, Jan et al. | 2012
- 189
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Convey vector personalities - FPGA acceleration with an openmp-like programming effort?Meyer, Bjorn / Schumacher, Jorn / Plessl, Christian / Forstner, Jens et al. | 2012
- 197
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Improving memory support in the VTR flowSomerville, Andrew / Kent, Kenneth B. et al. | 2012
- 203
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Verification of streaming designs by combining symbolic simulation and equivalence checkingTodman, Tim / Luk, Wayne et al. | 2012
- 209
-
Hardware implementation of MRF map inference on an FPGA platformChoi, Jungwook / Rutenbar, Rob A. et al. | 2012
- 217
-
CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filtersMahram, Atabak / Herbordt, Martin C. et al. | 2012
- 224
-
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP supportMatthews, Eric / Shannon, Lesley / Fedorova, Alexandra et al. | 2012
- 231
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Automating the design of mLUT MPSoPC FPGAs in the cloudCartwright, E. / Fahkari, A. / Ma, Sen / Smith, C. / Huang, M. / Andrews, D. / Agron, Jason et al. | 2012
- 237
-
A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functionsTakenaka, Takashi / Takagi, Masamichi / Inoue, Hiroaki et al. | 2012
- 243
-
Hardware implementation of motion blur removalChandrapala, T.N. / Cabral, L.M.A.P. / Ahangama, S. / Ambagahawaththa, T.S. / Samarawickrama, J.G. et al. | 2012
- 249
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Correctly rounded floating-point division for DSP-enabled FPGAsPasca, Bogdan et al. | 2012
- 255
-
Reduced complexity single and multiple constant multiplication in floating point precisionKumm, Martin / Liebisch, Katharina / Zipf, Peter et al. | 2012
- 262
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FPGA-based design and implementation of a multi-GBPS LDPC decoderBalatsoukas-Stimming, Alexios / Dollas, Apostolos et al. | 2012
- 270
-
Optimizing packet lookup in time and space on FPGAGanegedara, Thilan / Prasanna, Viktor / Brebner, Gordon et al. | 2012
- 277
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Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systemsBernardo, Rodrigo / Monte, Luis R. / Mobilon, Eduardo / Corso, Valentino / Salvador, Arley H. / Neves, Carolina G. / Nakandakare, Cleber A. / da Silva, Daniele R. / de Barros, Luis P. F. / da Silva, Ronaldo F. et al. | 2012
- 284
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High-level aging estimation for FPGA-mapped designsAmouri, Abdulazim / Tahoori, Mehdi et al. | 2012
- 292
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Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environmentsEspinosa, Jaime / de Andres, David / Carlos Ruiz, Juan / Gil, Pedro et al. | 2012
- 300
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Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systemsJacobs, Adam / Cieslewski, Grzegorz / George, Alan D. et al. | 2012
- 307
-
Automatically exploiting regularity in applications to reduce reconfiguration memory requirementsAbouelella, Fatma / Bruneel, Karel / Stroobandt, Dirk et al. | 2012
- 315
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Mapping logic to reconfigurable FPGA routingHeyse, Karel / Bruneel, Karel / Stroobandt, Dirk et al. | 2012
- 322
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Maximizing the reuse of routing resources in a reconfiguration-aware connection routerVansteenkiste, Elias / Bruneel, Karel / Stroobandt, Dirk et al. | 2012
- 330
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Random decision tree body part recognition using FPGAsOberg, Jason / Eguro, Ken / Bittner, Ray / Forin, Alessandro et al. | 2012
- 338
-
Acceleration of distance-to-default with hardware-software co-designAllugundu, Izaan / Puranik, Pranay / Lo, Yat Piu / Kumar, Akash et al. | 2012
- 345
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An efficient hardware architecture of the optimised SIFT descriptor generationDeng, Wenjuan / Zhu, Yiqun / Feng, Hao / Jiang, Zhiguo et al. | 2012
- 353
-
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable ArrayPanda, Robin / Ebeling, Carl / Hauck, Scott et al. | 2012
- 361
-
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment functionYoza, Takashi / Watanabe, Minoru et al. | 2012
- 367
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Non-volatile 3D stacking RRAM-based FPGAChen, Yi-Chung / Wang, Wenhua / Li, Hai / Zhang, Wei et al. | 2012
- 373
-
Intra-chip physical parameter sensor for FPGAS using flip-flop metastabilityTarawneh, Ghaith / Mak, Terrence / Yakovlev, Alex et al. | 2012
- 380
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A novel microprocessor-intrinsic Physical Unclonable FunctionMaiti, Abhranil / Schaumont, Patrick et al. | 2012
- 388
-
FPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligencePappala, Swetha / Niamat, Mohammed / Sun, Weiqing et al. | 2012
- 394
-
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGASRoca, Antoni / Flich, Jose / Dimitrakopoulos, Giorgos et al. | 2012
- 400
-
An area-efficient partially reconfigurable crossbar switch with low reconfiguration delayHoo, Chin Hau / Kumar, Akash et al. | 2012
- 407
-
An acceleration of a graph cut segmentation with FPGAKobori, Daichi / Maruyama, Tsutomu et al. | 2012
- 414
-
An FPGA acceleration of a level set segmentation methodTsuyama, Haruhisa / Maruyama, Tsutomu et al. | 2012
- 421
-
A high performance, open source SATA2 coreMendon, Ashwin A. / Huang, Bin / Sass, Ron et al. | 2012
- 429
-
IP-XACT extensions for IP interoperability guarantees and software model generationPerry, Thomas P. / Walke, Richard L. / Payne, Rob / Petko, Stefan / Benkrid, Khaled et al. | 2012
- 437
-
K-means implementation on FPGA for high-dimensional data using triangle inequalityLin, Zhongduo / Lo, Charles / Chow, Paul et al. | 2012
- 443
-
Enhancing performance of Tall-Skinny QR factorization using FPGAsRafique, Abid / Kapre, Nachiket / Constantinides, George A. et al. | 2012
- 451
-
Real-time corner and polygon detection system on FPGABi, Chunmeng / Maruyama, Tsutomu et al. | 2012
- 458
-
Deep-pipelined FPGA implementation of ellipse estimation for eye trackingDohi, Keisuke / Hatanaka, Yuma / Negi, Kazuhiro / Shibata, Yuichiro / Oguri, Kiyoshi et al. | 2012
- 464
-
A Benign Hardware Trojan on FPGA-based embedded systemsZheng, Jason X. / Chen, Ethan / Potkonjak, Miodrag et al. | 2012
- 471
-
A resiliency-aware scheduling approach for FPGA configuration: Preliminary resultsAbramson, Jeremy / Diniz, Pedro C. et al. | 2012
- 473
-
Power/performance optimization in FPGA-based asymmetric multi-core systemsSilva, Bruno de Abreu / Bonato, Vanderlei et al. | 2012
- 475
-
Thermal-aware partitioning for 3D FPGAsNunna, Krishna Chaitanya / Mehdipour, Farhad / Murakami, Kazuaki et al. | 2012
- 477
-
Reconfigurable multi-processor architecture for streaming applicationsGhazanfari, Leyla S. / Airoldi, Roberto / Nurmi, Jari / Ahonen, Tapani et al. | 2012
- 479
-
NoC-AXI interface for FPGA-based MPSoC platformsRamirez, Marco / Daneshtalab, Masoud / Plosila, Juha / Liljeberg, Pasi et al. | 2012
- 481
-
Modeling of dynamic reconfigurable systems with HaskellUchevler, Bahram N. / Svarstad, Kjetil et al. | 2012
- 483
-
Stimulation board for automated verification of touchscreen-based devicesKastelan, Ivan / Marinkovic, Vladimir / Dzakula, Radomir / Vranic, Nikola / Pekovic, Vukota et al. | 2012
- 485
-
High level structural description of streaming applicationsNiedermeier, Anja / Kuper, Jan / Smit, Gerard J.M. et al. | 2012
- 487
-
Ambient hardware and the case for transcoding media streamsOrlandic, Milica / Svarstad, Kjetil et al. | 2012
- 489
-
Combining data and computation transformations for fine-grain reconfigurable architecturesOliveira, Cristiano B. / Marques, Eduardo et al. | 2012
- 491
-
Implementation and outcomes of FPGA-based system design in Mongolian educationErdenechimeg, D. / Sugir, Ts. / Philipp, F. / Glesner, M. et al. | 2012
- 495
-
CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCSWang, Chao / Li, Xi / Zhang, Junneng / Chen, Peng / Zhou, Xuehai et al. | 2012
- 499
-
Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanismSawada, Junichi / Nishi, Hiroaki et al. | 2012
- 503
-
Dataflow graph partitioning for high level synthesisSinha, Sharad / Srikanthan, Thambipillai et al. | 2012
- 507
-
A fast and high quality stereo matching algorithm on FPGAJin, Minxi / Maruyama, Tsutomu et al. | 2012
- 511
-
An FPGA aligner for short read mappingChen, Yupeng / Schmidt, Bertil / Maksell, Douglas L. et al. | 2012
- 515
-
Raising the abstraction level of HDL for control-dominant applicationsDaigneault, Marc-Andre / David, Jean Pierre et al. | 2012
- 519
-
A two-stage variation-aware placement method for FPGAS exploiting variation maps classificationGuan, Zhenyu / Wong, Justin S. J. / Chaudhuri, Sumanta / Constantinides, George / Cheung, Peter Y. K. et al. | 2012
- 523
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Speedy bus mastering PCI expressBittner, Ray et al. | 2012
- 527
-
Adaptive Sequential Monte Carlo approach for real-time applicationsChau, Thomas C.P. / Luk, Wayne / Cheung, Peter Y.K. / Eele, Alison / Maciejowski, Jan et al. | 2012
- 531
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From opencl to high-performance hardware on FPGASCzajkowski, Tomasz S. / Aydonat, Utku / Denisenko, Dmitry / Freeman, John / Kinsner, Michael / Neto, David / Wong, Jason / Yiannacouras, Peter / Singh, Deshanand P. et al. | 2012
- 535
-
A framework for Open Tiled Manycore System-On-ChipWallentowitz, Stefan / Lankes, Andreas / Zaib, Aurang / Wild, Thomas / Herkersdorf, Andreas et al. | 2012
- 539
-
Fault detection and avoidance of FPGA in various granularitiesInoue, Kazuki / Nishitani, Yuki / Amagasaki, Motoki / Iida, Masahiro / Kuga, Morihiro / Sueyoshi, Toshinori et al. | 2012
- 543
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CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnectKoizumi, Yusuke / Sasaki, Eiichi / Amano, Hideharu / Matsutani, Hiroki / Take, Yasuhiro / Kuroda, Tadahiro / Sakamoto, Ryuichi / Namiki, Mitaro / Usami, Kimiyoshi / Kondo, Masaaki et al. | 2012
- 547
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Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfigurationSalvador, Ruben / Otero, Andres / Mora, Javier / de la Torre, Eduardo / Riesgo, Teresa / Sekanina, Lukas et al. | 2012
- 551
-
Development of an FPGA-based real-time P300 spellerKhurana, Kanav / Gupta, Pooja / Panicker, Rajesh C. / Kumar, Akash et al. | 2012
- 555
-
Influence of operating conditions on ring oscillator-based entropy sources in FPGAsHochberger, Christian / Li, Changgong / Raitza, Michael / Vogt, Markus et al. | 2012
- 559
-
Exploration of ring oscillator design space for temperature measurements on FPGAsRuething, Christoph / Agne, Andreas / Happe, Markus / Plessl, Christian et al. | 2012
- 563
-
Extending BORPH for shared memory reconfigurable computersChangqing, Xun / Mei, Wen / Nan, Wu / Chunyuan, Zhang / So, Hayden Kwok-Hay et al. | 2012
- 567
-
Automatic generation of application-specific accelerators for FPGAs from python loop nestsSheffield, David / Anderson, Michael / Keutzer, Kurt et al. | 2012
- 571
-
PPMC: Hardware scheduling and memory management support for multi acceleratorsHussain, Tassadaq / Pericas, Miquel / Navarro, Nacho / Ayguade, Eduard et al. | 2012
- 575
-
Performance analysis of fully-adaptable CRC accelerators on an FPGAAkagic, Amila / Amano, Hideharu et al. | 2012
- 579
-
Dynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filtersLlamocca, Daniel / Carranza, Cesar / Pattichis, Marios et al. | 2012
- 583
-
HCM: An abstraction layer for seamless programming of DPR FPGAXu, Yan / Muller, Olivier / Horrein, Pierre-Henri / Petrot, Frederic et al. | 2012
- 587
-
Early performance estimation of image compression methods on soft processorsPowell, Adam / Bouganis, Christos-S. / Cheung, Peter Y.K. et al. | 2012
- 591
-
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging systemKunz, Michael / Kumm, Martin / Heide, Martin / Zipf, Peter et al. | 2012
- 595
-
Sliding block Viterbi decoders in FPGAVestias, Mario / Neto, Horacio / Sarmento, Helena et al. | 2012
- 599
-
Dynamic query switching for complex event processing on FPGAsTakagi, Masamichi / Takenaka, Takashi / Inoue, Hiroaki et al. | 2012
- 603
-
Dual-core motion estimation processorOlivares, Joaquin / Palomares, Jose M. et al. | 2012
- 607
-
On the automatic integration of hardware accelerators into FPGA-based embedded systemsPilato, Christian / Cazzaniga, Andrea / Durelli, Gianluca / Otero, Andres / Sciuto, Donatella / Santambrogio, Marco D. et al. | 2012
- 611
-
Design of a novel Quantum-dot Cellular Automata Field Programmable Gate ArrayBalijepalli, Hemant / Niamat, Mohammed et al. | 2012
- 615
-
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architectureKameda, Toshihiro / Konoura, Hiroaki / Alnajjar, Dawood / Mitsuyama, Yukio / Hashimoto, Masanori / Onoye, Takao et al. | 2012
- 619
-
DWARV 2.0: A CoSy-based C-to-VHDL hardware compilerNane, Razvan / Sima, Vlad-Mihai / Olivier, Bryan / Meeuws, Roel / Yankova, Yana / Bertels, Koen et al. | 2012
- 623
-
Low area memory-free FPGA implementation of the AES algorithmChu, Junfeng / Benaissa, Mohammed et al. | 2012
- 627
-
An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfigurationHussain, Hanaa / Benkrid, Khaled / Hong, Chuan / Seker, Huseyin et al. | 2012
- 631
-
Fast digital rendering for special effectsCollinson, Sam / Morris, John et al. | 2012
- 635
-
Design and utilization of an FPGA cluster to implement a Digital Wireless Channel EmulatorBuscemi, Scott / Sass, Ron et al. | 2012
- 639
-
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAsTerada, Kazuhiko / Uzawa, Hiroyuki / Ikeda, Namiko / Shigematsu, Satoshi / Tanaka, Nobuyuki / Urano, Masami et al. | 2012
- 643
-
A new self-adapting architecture for feature detectionPossa, Paulo da Cunha / Mahmoudi, Sidi Ahmed / Harb, Naim / Valderrama, Carlos et al. | 2012
- 647
-
Custom instructions with local memory elements without expensive DMA transfersPrakash, Alok / Clarke, Christopher T. / Srikanthan, Thambipillai et al. | 2012
- 651
-
Dual MicroBlaze rekeying processor for group key managementGranado-Criado, Jose M. / Vega-Rodriguez, Miguel A. / Sanchez-Perez, Juan M. / Gomez-Pulido, Juan A. et al. | 2012
- 655
-
Lightweight reconfiguration security services for AXI-based MPSoCsCotret, Pascal / Gogniat, Guy / Diguet, Jean-Philippe / Crenne, Jeremie et al. | 2012
- 659
-
Examination of the concept of a row-column separated median filterWang, D. / Clarke, C. T. / Evans, A. N. et al. | 2012
- 663
-
On reconfigurable fabrics and generic side-channel countermeasuresBeat, R. / Grabher, P. / Page, D. / Tillich, S. / Wojcik, M. et al. | 2012
- 667
-
Hardware implementation of stereo correspondence algorithm for the ExoMars missionLentaris, G. / Diamantopoulos, D. / Siozios, K. / Soudris, D. / Rodrigalvarez, M. Aviles et al. | 2012
- 671
-
Design space exploration for automatically generated cryptographic hardware using functional languagesWolfs, Davy / Aerts, Kris / Mentens, Nele et al. | 2012
- 675
-
Fast and accurate Single Bit Error injection into SRAM Based FPGAsKretzschmar, U. / Astarloa, A. / Jimenez, J. / Garay, M. / Ser, J. Del et al. | 2012
- 679
-
(GECO)2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable ArchitecturePhilipp, Francois / Glesner, Manfred et al. | 2012
- 683
-
Design and implementation of fault-tolerant soft processors on FPGAsHong, Chuan / Benkrid, Khaled / Iturbe, Xabier / Ebrahim, Ali et al. | 2012
- 687
-
Towards GCC-based automatic soft-core customizationHempel, Gerald / Hochberger, Christian / Raitza, Michael et al. | 2012
- 691
-
An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminalsTraboulsi, Shadi / Zhang, Wenlong / Szczesny, Daivd / Showk, Anas / Bilgic, Attila et al. | 2012
- 695
-
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGAInggs, Gordon / Thomas, David / Winberg, Simon et al. | 2012
- 699
-
ITester: A FPGA based high performance traffic replay toolZhang, Fuxing / Xie, Yingke / Liu, Junjie / Luo, Layong / Ning, Qingsong / Wu, Xiaolong et al. | 2012
- 703
-
Modeling and synthesis of a Dynamic and Partial Reconfiguration controllerGuillet, S. / Lamotte, F. de / Griguer, N. Le / Rutten, E. / Diguet, J.-P. / Gogniat, G. et al. | 2012
- 707
-
An open-source design and validation platform for reconfigurable systemsBonetto, Alessandra / Cazzaniga, Andrea / Durelli, Gianluca / Pilato, Christian / Sciuto, Donatella / Santambrogio, Marco D. et al. | 2012
- 711
-
Floating point HOG implementation for real-time multiple object detectionKomorkiewicz, Mateusz / Kluczewski, Maciej / Gorgon, Marek et al. | 2012
- 715
-
Runtime reconfigurable DSP unit using one's complement and Minimum Signed DigitManderson, Travis / Turner, Laurence et al. | 2012
- 719
-
A high performance and low energy intra prediction hardware for High Efficiency Video CodingKalali, Ercan / Adibelli, Yusuf / Hamzaoglu, Ilker et al. | 2012
- 723
-
High-level linear projection circuit design optimization framework for FPGAs under over-clockingDuarte, Rui Policarpo / Bouganis, Christos-Savvas et al. | 2012
- 727
-
Evaluating the efficiency of DSP Block synthesis inference from flow graphsRonak, Bajaj / Fahmy, Suhaib A. et al. | 2012
- 731
-
System#: High-level synthesis of physical simulations for FPGA-based real-time executionKollner, Christian / Adler, Nico / Muller-Glaser, Klaus D. et al. | 2012
- 735
-
Bil: A tool-chain for bitstream reverse-engineeringBenz, Florian / Seffrin, Andre / Huss, Sorin A. et al. | 2012
- 739
-
A region merging approach for image segmentation on FPGATrieu, Dang Ba Khac / Maruyama, Tsutomu et al. | 2012
- 743
-
On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faultsPfeifer, Petr / Pliva, Zdenek et al. | 2012
- 747
-
Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGASKalenderi, Maria / Pnevmatikatos, Dionisios / Papaefstathiou, Ioannis / Manifavas, Charalampos et al. | 2012
- 754
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Index| 2012
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[Cover]| 2012