Defect-tolerant N2-transistor structure for reliable nanoelectronic designs (English)
- New search for: El-Maleh, A.H.
- New search for: Al-Hashimi, B.M.
- New search for: Melouki, A.
- New search for: Khan, F.
- New search for: El-Maleh, A.H.
- New search for: Al-Hashimi, B.M.
- New search for: Melouki, A.
- New search for: Khan, F.
In:
IET Computers & Digital Techniques
;
3
, 6
;
570-580
;
2009
- Article (Journal) / Electronic Resource
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Title:Defect-tolerant N2-transistor structure for reliable nanoelectronic designs
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Contributors:El-Maleh, A.H. ( author ) / Al-Hashimi, B.M. ( author ) / Melouki, A. ( author ) / Khan, F. ( author )
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Published in:IET Computers & Digital Techniques ; 3, 6 ; 570-580
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Publisher:
- New search for: The Institution of Engineering and Technology
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Publication date:2009-11-01
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Size:11 pages
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents – Volume 3, Issue 6
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 551
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Editorial: Advances in nanoelectronics circuits and systemsPaul, B.C. / Chakrabarty, K. et al. | 2009
- 553
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Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronicsMao, V. / Thusu, V. / Dwyer, C. / Chakrabarty, K. et al. | 2009
- 553
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Connecting fabrication defects to fault models and simulation program with integrated circuit emphasis simulations for DNA self-assembled nanoelectronicsMao, V. / Thusu, V. / Dwyer, C. / Chakrabarty, K. et al. | 2009
- 570
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Defect-tolerant N2-transistor structure for reliable nanoelectronic designsEl-Maleh, A.H. / Al-Hashimi, B.M. / Melouki, A. / Khan, F. et al. | 2009
- 581
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Is triple modular redundancy suitable for yield improvement?Vial, J. / Virazel, A. / Bosio, A. / Girard, P. / Landrault, C. / Pravossoudovitch, S. et al. | 2009
- 593
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Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designsDadgour, H.F. / Banerjee, K. et al. | 2009
- 609
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Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mappingChakraborty, R.S. / Paul, S. / Zhou, Y. / Bhunia, S. et al. | 2009
- 625
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Inversion schemes for sublithographic programmable logic arraysGojman, B. / Manem, H. / Rose, G.S. / DeHon, A. et al. | 2009
- 643
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Adaptive error control for nanometer scale network-on-chip linksYu, Q. / Ampadu, P. et al. | 2009