A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte-s Bandwidth (English)
- New search for: Yoo, J.-H.
- New search for: Yoo, J.-H.
- New search for: Kim, C.-H.
- New search for: Lee, K.-C.
- New search for: Kyung, K.-H.
- New search for: Yoo, S.-M.
- New search for: Lee, J.-H.
- New search for: Son, M.-H.
- New search for: Han, J.-M.
- New search for: Kang, B.-M.
- New search for: Haq, E.
- New search for: Lee, S.-B.
- New search for: Sim, J.-H.
- New search for: Kim, J.-H.
- New search for: Moon, B.-S.
- New search for: Kim, K.-Y.
- New search for: Park, J.-G.
- New search for: Lee, K.-P.
- New search for: Lee, K.-Y.
- New search for: Kim, K.-N.
In:
IEEE journal of solid state circuits
;
31
, 11
; 1635-1644
;
1996
-
ISSN:
- Article (Journal) / Print
-
Title:A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte-s Bandwidth
-
Contributors:Yoo, J.-H. ( author ) / Kim, C.-H. / Lee, K.-C. / Kyung, K.-H. / Yoo, S.-M. / Lee, J.-H. / Son, M.-H. / Han, J.-M. / Kang, B.-M. / Haq, E.
-
Published in:IEEE journal of solid state circuits ; 31, 11 ; 1635-1644
-
Publisher:
- New search for: IEEE
-
Place of publication:New York, NY
-
Publication date:1996
-
ISSN:
-
ZDBID:
-
Type of media:Article (Journal)
-
Type of material:Print
-
Language:English
- New search for: 770/5670
- New search for: 53.55 / 33.72 / 53.56 / 53.51
- Further information on Basic classification
-
Keywords:
-
Classification:
-
Source:
Table of contents – Volume 31, Issue 11
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1571
-
Special Issue on the 1996 ISSCC: Memory, Digital, and Signal ProcessingGillingham, P. et al. | 1996
- 1571
-
Special Issue on the 1996 ISSCC: Memory, Digital, and Signal Processing [Editorial]Gillingham, P. / Bowhill, W. / Noll, T.G. et al. | 1996
- 1575
-
A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage ApplicationsJung, T.-S. et al. | 1996
- 1584
-
A 98 mm2 Die Size 3.3-V 64-Mb Flash Memory with FN-NOR Type Four-Level CellOhkawa, M. et al. | 1996
- 1590
-
Bit-Line Clamped Sensing Multiplex and Accurate High Voltage Generator for Quarter-Micron Flash MemoriesKawahara, T. et al. | 1996
- 1601
-
A 1-Mb 2-Tr-b Nonvolatile CAM Based on Flash Memory TechnologiesMiwa, T. et al. | 1996
- 1610
-
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAMToyoshima, H. et al. | 1996
- 1618
-
A 1-V, 100-MHz, 10-mW Cache Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag ComparatorsMizuno, H. et al. | 1996
- 1625
-
A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with a Nondriven Cell Plate Line Write-Read SchemeKoike, H. et al. | 1996
- 1635
-
A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte-s BandwidthYoo, J.-H. et al. | 1996
- 1645
-
A 1.6-GB-s Data-Rate 1-Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank ArchitectureSakashita, N. et al. | 1996
- 1656
-
A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror DelaySaeki, T. et al. | 1996
- 1669
-
Design of a one-transistor-cell multiple-valued CAMHanyu, T. / Kanagawa, N. / Kameyama, M. et al. | 1996
- 1675
-
200-MHz Superscalar RISC MicroprocessorVasseghi, N. et al. | 1996
- 1687
-
A 433-MHz 64-b Quad-Issue RISC MicroprocessorGronowski, P.E. et al. | 1996
- 1697
-
A 64-b Quad-Issue CMOS RISC MicroprocessorGaddis, N. et al. | 1996
- 1703
-
A 160-MHz, 32-b, 0.5-W CMOS RISC MicroprocessorMontanaro, J. et al. | 1996
- 1715
-
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock GenerationKaenel, V.von et al. | 1996
- 1723
-
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased TechniquesManeatis, J.G. et al. | 1996
- 1733
-
A Real-Time Motion Estimation and Compensation LSI with Wide Search Range for MPEG2 Video EncodingSuguri, K. et al. | 1996
- 1742
-
A 14-Gops Programmable Motion Estimator For H.26X Video CodingLin, H.-D. et al. | 1996
- 1751
-
A 64-Point Fourier Transform Chip for Video Motion Compensation Using Phase CorrelationHui, C.C.W. et al. | 1996
- 1762
-
A Video Signal Processor for Motion-Compensated Field-Rate Upconversion in Consumer TelevisionLippens, P. et al. | 1996
- 1770
-
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) SchemeKuroda, T. et al. | 1996
- 1780
-
Low-Power Video Encoder-Decoder Chip Set for Digital VCR'sHasegawa, K. et al. | 1996
- 1789
-
A Low Power Video-Rate Pyramid VQ DecoderTsern, E.K. et al. | 1996
- 1795
-
A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone ApplicationMutoh, S. et al. | 1996
- 1803
-
A 160-MHz Analog Front-End IC for EPR-IV PRML Magnetic Storage Read ChannelsPai, P.K.D. et al. | 1996
- 1817
-
A PRML Read-Write Channel IC Using Analog Signal Processing for 200 Mb-s HDDParsi, K. et al. | 1996
- 1831
-
A CMOS 6-b, 200 MSample-s, 3 V-Supply A-D Converter for a PRML Read Channel LSITsukamoto, S. et al. | 1996