Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions (English)
- New search for: Drechsler, R.
- New search for: Drechsler, R.
- New search for: Becker, B.
In:
IEEE transactions on computer-aided design of integrated circuits and systems
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16
, 1
; 1-5
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1997
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ISSN:
- Article (Journal) / Print
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Title:Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions
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Contributors:Drechsler, R. ( author ) / Becker, B.
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Published in:
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:1997
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 770/3155/5670
- New search for: 53.52 / 33.72 / 33.61 / 53.51
- Further information on Basic classification
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Keywords:
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Classification:
Local classification TIB: 770/3155/5670 BKL: 53.52 Elektronische Schaltungen / 33.72 Halbleiterphysik / 33.61 Festkörperphysik / 53.51 Bauelemente der Elektronik -
Source:
Table of contents – Volume 16, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric FunctionsDrechsler, R. et al. | 1997
- 6
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Transmission Line Synthesis via Constrained Multivariable OptimizationGupta, R. et al. | 1997
- 20
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Routing for Symmetric FPGA's and FPIC'sSun, Y. et al. | 1997
- 32
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Algorithms for an FPGA Switch Module Routing Problem with Application to Global RoutingThakur, S. et al. | 1997
- 47
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On-Line Testing of Statically and Dynamically Scheduled Synthesized SystemsBrown, A.D. et al. | 1997
- 58
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Optimal Testing of VLSI Analog CircuitsChao, C.-Y. et al. | 1997
- 78
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On the Fault Coverage of Gate Delay Fault Detecting TestsPramanick, A. K. / Reddy, S. M. et al. | 1997
- 78
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On die Fault Coverage of Gate Delay Fault Detecting TestsPramanick, A.K. et al. | 1997
- 95
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The Elmore Delay as a Bound for RC Trees with Generalized Input SignalsCupta, R. et al. | 1997
- 105
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Incorporating Interconnect, Register, and Clock Distribution Delays into the Retiming ProcessSoyata, T. et al. | 1997
- 121
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Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic SimulationMonteiro, J. et al. | 1997
- 128
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34th Design Automation Conference| 1997
- 129
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Call for Participation -- International Symposium on Low Power Electronics and Design| 1997
- 130
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Call for Papers and Participation -- Eleventh International Conference on VLSI Design| 1997
- 131
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IEEE Copyright Form| 1997