Testing - Simulating Resistive-Bridging and Stuck-At Faults (English)
- New search for: Engelke, P.
- New search for: Engelke, P.
- New search for: Polian, I.
- New search for: Renovell, M.
- New search for: Becker, B.
In:
IEEE transactions on computer-aided design of integrated circuits and systems
;
25
, 10
; 2181-2192
;
2006
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ISSN:
- Article (Journal) / Print
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Title:Testing - Simulating Resistive-Bridging and Stuck-At Faults
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Contributors:
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Published in:IEEE transactions on computer-aided design of integrated circuits and systems ; 25, 10 ; 2181-2192
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2006
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 770/3155/5670
- New search for: 53.52 / 33.72 / 33.61 / 53.51
- Further information on Basic classification
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Keywords:
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Classification:
Local classification TIB: 770/3155/5670 BKL: 53.52 Elektronische Schaltungen / 33.72 Halbleiterphysik / 33.61 Festkörperphysik / 53.51 Bauelemente der Elektronik -
Source:
Table of contents – Volume 25, Issue 10
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1889
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Placement Algorithm in Analog-Layout DesignsLihong Zhang, / Raut, R. / Yingtao Jiang, / Kleine, U. et al. | 2006
- 1889
-
Analog Layout - Placement Algorithm in Analog-Layout DesignsZhang, L. et al. | 2006
- 1904
-
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous SpecificationsCortadella, J. / Kondratyev, A. / Lavagno, L. / Sotiriou, C.P. et al. | 2006
- 1904
-
Asynchronous Circuits - Desynchronization: Synthesis of Asynchronous Circuits From Synchronous SpecificationsCortadella, J. et al. | 2006
- 1922
-
Design-Intent Coverage—A New Paradigm for Formal Property VerificationBasu, P. / Das, S. / Banerjee, A. / Dasgupta, P. / Chakrabarti, P.P. / Mohan, C.R. / Fix, L. / Armoni, R. et al. | 2006
- 1922
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Formal Verification - Design-Intent Coverage -- A New Paradigm for Formal Property VerificationBasu, P. et al. | 2006
- 1922
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Design-Intent Coverage-A New Paradigm for Formal Property VerificationBasu, P. / Das, S. / Banerjee, A. / Dasgupta, P. / Chakrabarti, P. P. / Mohan, C. R. / Fix, L. / Armoni, R. et al. | 2006
- 1935
-
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-EmulationJae-Gon Lee, / Chong-Min Kyung, et al. | 2006
- 1935
-
Hardware-Software Co-Design - PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware-Software Co-EmulationLee, J.-G. et al. | 2006
- 1950
-
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA ImplementationsBilavarn, S. / Gogniat, G. / Philippe, J.-L. / Bossuet, L. et al. | 2006
- 1950
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High-Level Synthesis - Design Space Pruning Through Early Estimations of Area-Delay Tradeoffs for FPGA ImplementationsBilavarn, S. et al. | 2006
- 1969
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Use of Computation-Unit Integrated Memories in High-Level SynthesisChao Huang, / Ravi, S. / Raghunathan, A. / Jha, N.K. et al. | 2006
- 1969
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High-Level Synthesis - Use of Computation-Unit Integrated Memories in High-Level SynthesisHuang, C. et al. | 2006
- 1990
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High-Level Synthesis - Accuracy-Guaranteed Bit-Width OptimizationLee, D.-U. et al. | 2006
- 1990
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Accuracy-Guaranteed Bit-Width OptimizationLee, D.-U. / Gaffar, A.A. / Cheung, R.C.C. / Mencer, O. / Luk, W. / Constantinides, G.A. et al. | 2006
- 2001
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Hermite Polynomial Based Interconnect Analysis in the Presence of Process VariationsVrudhula, S. / Wang, J.M. / Ghanta, P. et al. | 2006
- 2001
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Interconnect Analysis - Hermite Polynomial Based Interconnect Analysis in the Presence of Process VariationsVrudhula, S. et al. | 2006
- 2012
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Logic Synthesis - Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression EliminationHosangadi, A. et al. | 2006
- 2012
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Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression EliminationHosangadi, A. / Fallah, F. / Kastner, R. et al. | 2006
- 2023
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Low-Power Design - Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power ReductionLin, Y. et al. | 2006
- 2023
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Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power ReductionLin, Y. / Lei He, et al. | 2006
- 2035
-
Low-Power Design - Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded SystemsVerma, M. et al. | 2006
- 2035
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Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded SystemsVerma, M. / Wehmeyer, L. / Marwedel, P. et al. | 2006
- 2052
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Modeling - Modeling and Analysis of Leakage Currents in Double-Gate TechnologiesMukhopadhyay, S. et al. | 2006
- 2052
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Modeling and Analysis of Leakage Currents in Double-Gate TechnologiesMukhopadhyay, S. / Keunwoo Kim, / Ching Te Chuang, / Roy, K. et al. | 2006
- 2062
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Two Algorithms for Fast and Accurate Passivity-Preserving Model Order ReductionNgai Wong, / Balakrishnan, V. / Cheng-Kok Koh, / Tung-Sang Ng, et al. | 2006
- 2062
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Model Order Reduction - Two Algorithms for Fast and Accurate Passivity-Preserving Model Order ReductionWong, N. et al. | 2006
- 2076
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Force-Directed Methods for Generic PlacementKennings, A. / Vorwerk, K.P. et al. | 2006
- 2076
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Physical Design - Force-Directed Methods for Generic PlacementKennings, A. et al. | 2006
- 2088
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Statistical Analysis and Design of HARP FPGAsGang Wang, / Sivaswamy, S. / Ababei, C. / Bazargan, K. / Kastner, R. / Bozorgzadeh, E. et al. | 2006
- 2088
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Physical Design - Statistical Analysis and Design of HARP FPGAsWang, G. et al. | 2006
- 2103
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Power Estimation - RTL-Aware Cycle-Accurate Functional Power EstimationZhong, L. et al. | 2006
- 2103
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RTL-Aware Cycle-Accurate Functional Power EstimationLin Zhong, / Ravi, S. / Raghunathan, A. / Jha, N.K. et al. | 2006
- 2118
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Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential EquationsCervenka, J. / Wessner, W. / Al-Ani, E. / Grasser, T. / Selberherr, S. et al. | 2006
- 2118
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Process-Device Simulation - Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential EquationsCervenka, J. et al. | 2006
- 2129
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Process-Device Simulation - Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing ProcessesWessner, W. et al. | 2006
- 2129
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Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing ProcessesWessner, W. / Cervenka, J. / Heitzinger, C. / Hossinger, A. / Selberherr, S. et al. | 2006
- 2140
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Soft-Error-Rate-Analysis (SERA) MethodologyMing Zhang, / Shanbhag, N.R. et al. | 2006
- 2140
-
Soft-Error-Rate Analysis - Soft-Error-Rate-Analysis (SERA) MethodologyZhang, M. et al. | 2006
- 2156
-
Voltage-Aware Static Timing AnalysisKouroussis, D. / Ahmadi, R. / Najm, F.N. et al. | 2006
- 2156
-
Static Timing Analysis - Voltage-Aware Static Timing AnalysisKouroussis, D. et al. | 2006
- 2170
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First-Order Incremental Block-Based Statistical Timing AnalysisVisweswariah, C. / Ravindran, K. / Kalafala, K. / Walker, S.G. / Narayan, S. / Beece, D.K. / Piaget, J. / Venkateswaran, N. / Hemmett, J.G. et al. | 2006
- 2170
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Statistical Timing Analysis - First-Order Incremental Block-Based Statistical Timing AnalysisVisweswariah, C. et al. | 2006
- 2181
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Simulating Resistive-Bridging and Stuck-At FaultsPiet Engelke, / Polian, I. / Renovell, M. / Becker, B. et al. | 2006
- 2181
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Testing - Simulating Resistive-Bridging and Stuck-At FaultsEngelke, P. et al. | 2006
- 2193
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Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression TechniquesLingappan, L. / Ravi, S. / Raghunathan, A. / Jha, N.K. / Chakradhar, S.T. et al. | 2006
- 2193
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Testing - Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression TechniquesLingappan, L. et al. | 2006
- 2207
-
Generation of Functional Broadside Tests for Transition FaultsPomeranz, I. / Reddy, S.M. et al. | 2006
- 2207
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Testing - Generation of Functional Broadside Tests for Transition FaultsPomeranz, I. et al. | 2006
- 2219
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Using Dummy Bridging Faults to Define Reduced Sets of Target FaultsPomeranz, I. / Reddy, S.M. et al. | 2006
- 2219
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Testing - Using Dummy Bridging Faults to Define Reduced Sets of Target FaultsPomeranz, I. et al. | 2006
- 2228
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A Metric for Automatic Word-Length Determination of Hardware DatapathsCantin, M.-A. / Savaria, Y. / Prodanos, D. / Lavoie, P. et al. | 2006
- 2228
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SHORT PAPERS - A Metric for Automatic Word-Length Determination of Hardware DatapathsCantin, M.-A. et al. | 2006
- 2231
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Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal InteractionsCapobianchi, M. / Labay, V. / Fong Shi, / Mizushima, G. et al. | 2006
- 2231
-
SHORT PAPERS - Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal InteractionsCapobianchi, M. et al. | 2006
- 2241
-
Testability of SPP Three-Level Logic Networks in Static Fault ModelsCiriani, V. / Bernasconi, A. / Drechsler, R. et al. | 2006
- 2241
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SHORT PAPERS - Testability of SPP Three-Level Logic Networks in Static Fault ModelsCiriani, V. et al. | 2006
- 2248
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Block-level 3-D Global Routing With an Application to 3-D PackagingMinz, J. / Sung Kyu Lim, et al. | 2006
- 2248
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SHORT PAPERS - Block-Level 3-D Global Routing With an Application to 3-D PackagingMinz, J. et al. | 2006
- 2258
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RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay ReductionShang-Wei Tu, / Yao-Wen Chang, / Jing-Yang Jou, et al. | 2006
- 2258
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SHORT PAPERS - RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay ReductionTu, S.-W. et al. | 2006
- 2264
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Modeling the Driver Load in the Presence of Process VariationsWang, J.M. / Jun Li, / Yanamanamanda, S. / Vakati, L.K. / Muchherla, K.K. et al. | 2006
- 2264
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SHORT PAPERS - Modeling the Driver Load in the Presence of Process VariationsWang, J.M. et al. | 2006
- 2275
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State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design ValidationQingwei Wu, / Hsiao, M.S. et al. | 2006
- 2275
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SHORT PAPERS - State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design ValidationWu, Q. et al. | 2006
- 2282
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SHORT PAPERS - Fast 3-D Capacitance Extraction by Inexact Factorization and ReductionYan, S. et al. | 2006
- 2282
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Fast 3-D Capacitance Extraction by Inexact Factorization and ReductionYan, S. / Sarin, V. / Weiping Shi, et al. | 2006
- 2287
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Secure Scan: A Design-for-Test Architecture for Crypto ChipsBo Yang, / Kaijie Wu, / Karri, R. et al. | 2006
- 2287
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SHORT PAPERS - Secure Scan: A Design-for-Test Architecture for Crypto ChipsYang, B. et al. | 2006
- 2294
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2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)| 2006
- 2294
-
ANNOUNCEMENTS - Preliminary Call for Papers: IEEE ISCAS 2007| 2006
- 2295
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Special issue on systems biology| 2006
- 2295
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ANNOUNCEMENTS - Call for Papers for T-AC and T-CAS1: Joint Special Issue on Systems Biology| 2006
- 2296
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors| 2006
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Table of contents| 2006
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information| 2006
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information| 2006