Modeling and Simulation - Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting (English)
- New search for: Zhao, X
- New search for: Zhao, X
- New search for: Guo, Y
- New search for: Chen, X
- New search for: Feng, Z
- New search for: Hu, S
In:
IEEE transactions on computer-aided design of integrated circuits and systems
;
30
, 11
; 1610-1621
;
2011
-
ISSN:
- Article (Journal) / Print
-
Title:Modeling and Simulation - Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting
-
Contributors:
-
Published in:IEEE transactions on computer-aided design of integrated circuits and systems ; 30, 11 ; 1610-1621
-
Publisher:
- New search for: Institute of Electrical and Electronics Engineers
-
Place of publication:New York, NY
-
Publication date:2011
-
ISSN:
-
ZDBID:
-
Type of media:Article (Journal)
-
Type of material:Print
-
Language:English
- New search for: 770/3155/5670
- New search for: 53.52 / 33.72 / 33.61 / 53.51
- Further information on Basic classification
-
Keywords:
-
Classification:
Local classification TIB: 770/3155/5670 BKL: 53.52 Elektronische Schaltungen / 33.72 Halbleiterphysik / 33.61 Festkörperphysik / 53.51 Bauelemente der Elektronik -
Source:
Table of contents – Volume 30, Issue 11
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1585
-
System-Level Online Power Estimation Using an On-Chip Bus Performance Monitoring UnitYounghyun Kim, / Sangyoung Park, / Youngjin Cho, / Naehyuck Chang, et al. | 2011
- 1585
-
Embedded Systems - System-Level Online Power Estimation Using an On-Chip Bus Performance Monitoring UnitKim, Y et al. | 2011
- 1599
-
High Throughput Data Mapping for Coarse-Grained Reconfigurable ArchitecturesYongjoo Kim, / Jongeun Lee, / Shrivastava, A. / Yoon, J. W. / Doosan Cho, / Yunheung Paek, et al. | 2011
- 1599
-
FPGAs and Reconfigurable Computing - High Throughput Data Mapping for Coarse-Grained Reconfigurable ArchitecturesKim, Y et al. | 2011
- 1610
-
Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap BudgetingXueqian Zhao, / Yonghe Guo, / Xiaodao Chen, / Zhuo Feng, / Shiyan Hu, et al. | 2011
- 1610
-
Modeling and Simulation - Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap BudgetingZhao, X et al. | 2011
- 1621
-
High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine LearningDuo Ding, / Torres, J. A. / Pan, D. Z. et al. | 2011
- 1621
-
Physical Design - High Performance Lithography Hotspot Detection with Successively Refined Pattern Identifications and Machine LearningDing, D et al. | 2011
- 1635
-
Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICsYoung-Joon Lee, / Sung Kyu Lim, et al. | 2011
- 1649
-
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit DesignsYi-Lin Chuang, / Po-Wei Lee, / Yao-Wen Chang, et al. | 2011
- 1663
-
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing AlgorithmJain, T. N. K. / Ramakrishna, M. / Gratz, P. V. / Sprintson, A. / Gwan Choi, et al. | 2011
- 1663
-
System-Level Design - Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing AlgorithmJain, T N K et al. | 2011
- 1677
-
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core ProcessorsHanumaiah, V. / Vrudhula, S. / Chatha, K. S. et al. | 2011
- 1691
-
Bounding Variable Values and Round-Off Effects Using Handelman RepresentationsBoland, D. / Constantinides, G. A. et al. | 2011
- 1705
-
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICsNoia, B. / Chakrabarty, K. / Goel, S. K. / Marinissen, E. J. / Verbree, J. et al. | 2011
- 1705
-
Test - Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICsNoia, B et al. | 2011
- 1719
-
A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge DefectsShida Zhong, / Khursheed, S. / Al-Hashimi, B. M. et al. | 2011
- 1731
-
Memory Built-in Self-Repair Planning Framework for RAMs in SoCsChih-Sheng Hou, / Jin-Fu Li, / Tsu-Wei Tseng, et al. | 2011
- 1744
-
Unified 2-D X-Alignment for Improving the Observability of Response CompactorsSinanoglu, O. / Almukhaizim, S. et al. | 2011
- 1758
-
SHORT PAPERS - Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing AnalysisForeman, E A et al. | 2011
- 1758
-
Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing AnalysisForeman, E. A. / Habitz, P. A. / Cheng, M-C / Tamon, C. et al. | 2011
- 1762
-
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault TestingZhen Chen, / Chakrabarty, K. / Dong Xiang, et al. | 2011
- 1767
-
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality ObjectivesKuan-Yu Liao, / Chia-Yuan Chang, / Li, J. C-M et al. | 2011
- C1
-
Table of contents| 2011
- C2
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information| 2011
- C3
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information| 2011
- C4
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors| 2011