A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System (English)
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In:
IEEE transactions on circuits and systems / 2
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60
, 1
; 6-10
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2013
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ISSN:
- Article (Journal) / Print
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Title:A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System
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Contributors:
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Published in:IEEE transactions on circuits and systems / 2 ; 60, 1 ; 6-10
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2013
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 60, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery SystemsIhm, Jae-Yong et al. | 2013
- 1
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Analog and Mixed Mode Circuits and Systems - Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery SystemsIhm, J-Y et al. | 2013
- 6
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A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface SystemKim, Sunkwon / Woo, Jong-Kwan / Shin, Woo-Yeol / Hong, Gi-Moon / Lee, Hyongmin / Lee, Hyunjoong / Kim, Suhwan et al. | 2013
- 11
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A Fifth-Order 20-MHz Transistorized-$LC$ -Ladder LPF With 58.2-dB SFDR, 68-$\mu\hbox{W/Pole/MHz}$ Efficiency, and 0.13-$\hbox{mm}^{2}$ Die Size in 90-nm CMOSChen, Yong / Mak, Pui-In / Zhang, Li / Qian, He / Wang, Yan et al. | 2013
- 11
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A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm2 Die Size in 90-nm CMOSChen, Y et al. | 2013
- 11
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A Fifth-Order 20-MHz Transistorized- Formula Not Shown -Ladder LPF With 58.2-dB SFDR, 68- Formula Not Shown Efficiency, and 0.13- Formula Not Shown Die Size in 90-nm CMOSChen, Y. / Mak, P. I. / Zhang, L. / Qian, H. / Wang, Y. et al. | 2013
- 16
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Low-Power High Parallel Load Resistance Current-Mode Grounded and Floating Capacitor MultiplierPadilla-Cantoya, Ivan et al. | 2013
- 21
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A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCDLee, Won-Young / Oh, Jiehwan / Kim, Lee-Sup et al. | 2013
- 26
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Memoryless Wide-Dynamic-Range CMOS Image Sensor Using Nonfully Depleted PPD-Storage Dual CaptureLee, Jiwon / Baek, Inkyu / Yang, Kyounghoon et al. | 2013
- 31
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Digital Circuits and Systems and VLSI - VLSI Implementation of a Low-Cost High-Quality Image Scaling ProcessorChen, S-L et al. | 2013
- 31
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VLSI Implementation of a Low-Cost High-Quality Image Scaling ProcessorChen, Shih-Lun et al. | 2013
- 36
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FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area NetworkWang, Yi / Ha, Yajun et al. | 2013
- 41
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High-Performance Implementation of Point Multiplication on Koblitz CurvesAzarderakhsh, Reza / Reyhani-Masoleh, Arash et al. | 2013
- 46
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Signal Processing - Joint DOA Estimation and Source Signal Tracking With Kalman Filtering and Regularized QRD RLS AlgorithmGu, J-F et al. | 2013
- 46
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Joint DOA Estimation and Source Signal Tracking With Kalman Filtering and Regularized QRD RLS AlgorithmGu, Jian-Feng / Chan, S. C. / Zhu, Wei-Ping / Swamy, M. N. S. et al. | 2013
- 51
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Initiation of Characteristic Ferroresonance States Based on Flux Reflection ModelMilicevic, Kruno / Emin, Zia et al. | 2013
- 51
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Nonlinear Circuits and Systems - Initiation of Characteristic Ferroresonance States Based on Flux Reflection ModelMilicevic, K et al. | 2013
- 56
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Comments on “A Note on Observers for Discrete-Time Lipschitz Nonlinear Systems”Zemouche, Ali / Boutayeb, Mohamed et al. | 2013
- C1
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Table of Contents| 2013
- C2
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IEEE Transactions on Circuits and Systems—II: Express Briefs publication information| 2013
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IEEE Circuits and Systems Society Information| 2013
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IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors| 2013