Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs (English)
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IEEE transactions on very large scale integration (VLSI) systems
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21
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; 1863-1877
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2013
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ISSN:
- Article (Journal) / Print
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Title:Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 21, 10 ; 1863-1877
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- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2013
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 21, Issue 10
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1769
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Enhancing the Efficiency of Energy-Constrained DVFS DesignsKahng, Andrew B. / Kang, Seokhyeong / Kumar, Rakesh / Sartori, John et al. | 2013
- 1769
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Low Power Design - Enhancing the Efficiency of Energy-Constrained DVFS DesignsKahng, A B et al. | 2013
- 1783
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Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage MinimizationHwang, Eun Ju / Kim, Wook / Kim, Young Hwan et al. | 2013
- 1797
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Embedded Transition Inversion Coding With Low Switching Activity for Serial LinksChiu, Ching-Te / Huang, Wen-Chih / Lin, Chih-Hsing / Lai, Wei-Chih / Tsao, Ying-Fang et al. | 2013
- 1811
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Testing and Verification - Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process VariationNarayanan, R et al. | 2013
- 1811
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Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process VariationNarayanan, Rajeev / Seghaier, Ibtissem / Zaki, Mohamed H. / Tahar, Sofiene et al. | 2013
- 1823
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Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-ChipXie, Yiyuan / Nikdast, Mahdi / Xu, Jiang / Wu, Xiaowen / Zhang, Wei / Ye, Yaoyao / Wang, Xuan / Wang, Zhehui / Liu, Weichen et al. | 2013
- 1837
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CASSER: A Closed-Form Analysis Framework for Statistical Soft Error RateChang, Austin C.-C. / Huang, Ryan H.-M. / Wen, Charles H.-P. et al. | 2013
- 1849
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Architectural Design - Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor ProcessorsShoaib, M et al. | 2013
- 1849
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Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor ProcessorsShoaib, Mohammed / Jha, Niraj K. / Verma, Naveen et al. | 2013
- 1863
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Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPsKim, Hyunhee / Ahn, Jung Ho / Kim, Jihong et al. | 2013
- 1878
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Novel Bio-Inspired Approach for Fault-Tolerant VLSI SystemsSamie, Mohammad / Dragffy, Gabriel / Tyrrell, Andy M. / Pipe, Tony / Bremner, Paul et al. | 2013
- 1878
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Reliable Design - Novel Bio-Inspired Approach for Fault-Tolerant VLSI SystemsSamie, M et al. | 2013
- 1892
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New Crosstalk Avoidance Codes Based on a Novel Pattern ClassificationShi, Feng / Wu, Xuebin / Yan, Zhiyuan et al. | 2013
- 1903
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Mitigating the Impact of Process Variation on the Performance of 3-D Integrated CircuitsGarg, Siddharth / Marculescu, Diana et al. | 2013
- 1915
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Reconfigurable Systems - Design and Evaluation of High-Performance Processing Elements for Reconfigurable SystemsPurohit, S S et al. | 2013
- 1915
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Design and Evaluation of High-Performance Processing Elements for Reconfigurable SystemsPurohit, Sohan S. / Chalamalasetti, Sai Rahul / Margala, Martin / Vanderbauwhede, Wim A. et al. | 2013
- 1928
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1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback TechniqueDai, Shanshan / Cao, Xiaofei / Yi, Ting / Hubbard, Allyn E. / Hong, Zhiliang et al. | 2013
- 1928
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Analog Design - 1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback TechniqueDai, S et al. | 2013
- 1936
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Efficient VLSI Implementation of Formula Not Shown Scaling of Signed Integer in RNS Formula Not ShownTay, T. F. / Chang, C. H. / Low, J. Y. et al. | 2013
- 1936
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BRIEF PAPERS - Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1,2n,2n + l}Tay, T F et al. | 2013
- 1936
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Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n},2^{n}+1\}}$Tay, Thian Fatt / Chang, Chip-Hong / Low, Jeremy Yung Shern et al. | 2013
- 1941
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Integrated Power and Clock Distribution NetworkEsmaeili, Seyed E. / Al-Kahlili, Asim J. et al. | 2013
- 1945
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On the Design of RNS Reverse Converters for the Four-Moduli Set Formula Not ShownSousa, L. / Antao, S. / Chaves, R. et al. | 2013
- 1945
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On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$Sousa, Leonel / Antao, Samuel / Chaves, Ricardo et al. | 2013
- 1945
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On the Design of RNS Reverse Converters for the Four-Moduli Set {2n + 1,2n - 1,2n,2n+1 + 1}Sousa, L et al. | 2013
- 1950
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366-kS/s 1.09-nJ 0.0013-mm2 Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase ClockKim, K et al. | 2013
- 1950
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366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase ClockKim, Kisoo / Lee, Hokyu / Kim, Chulwoo et al. | 2013
- 1950
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366-kS/s 1.09-nJ 0.0013- Formula Not Shown Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase ClockKim, K. / Lee, H. / Kim, C. et al. | 2013
- 1955
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Sparsification of Dense Capacitive Coupling of Interconnect ModelsMiettinen, Pekka / Honkala, Mikko / Roos, Janne / Valtonen, Martti et al. | 2013
- 1960
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VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant WeightSun, Yang / Cavallaro, Joseph R. et al. | 2013
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Table of contents| 2013
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2013
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2013