Exploring High-Throughput Computing Paradigm for Global Routing (English)
- New search for: Han, Y
- New search for: Han, Y
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In:
IEEE transactions on very large scale integration (VLSI) systems
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22
, 1
; 155-167
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2014
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ISSN:
- Article (Journal) / Print
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Title:Exploring High-Throughput Computing Paradigm for Global Routing
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 22, 1 ; 155-167
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2014
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 22, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS AmplifiersMukadam, Mustansir Y. / Gouveia-Filho, Oscar C. / Kramer, Nicholas / Zhang, Xuan / Apsel, Alyssa B. et al. | 2014
- 1
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Low Power Design - Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS AmplifiersMukadam, M Y et al. | 2014
- 13
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Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power SwitchesZhang, Zhaobo / Kavousianos, Xrysovalantis / Chakrabarty, Krishnendu / Tsiatouhas, Yiorgos et al. | 2014
- 27
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Stability Estimation of a 6T-SRAM Cell Using a Nonlinear RegressionPark, Henry / Yang, Chih-Kong Ken et al. | 2014
- 27
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Memories - Stability Estimation of a 6T-SRAM Cell Using a Nonlinear RegressionPark, H et al. | 2014
- 39
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Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation FunctionZamanlooy, Babak / Mirhassani, Mitra et al. | 2014
- 39
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VLSI Design - Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation FunctionZamanlooy, B et al. | 2014
- 49
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Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element ArchitectureLee, Jen-Wei / Chung, Szu-Chi / Chang, Hsie-Chia / Lee, Chen-Yi et al. | 2014
- 49
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Architectural Design - Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element ArchitectureLee, J-W et al. | 2014
- 62
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Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set ExtensionsKluter, Theo / Brisk, Philip / Charbon, Edoardo / Ienne, Paolo et al. | 2014
- 76
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High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video ApplicationsHe, Gang / Zhou, Dajiang / Fei, Wei / Chen, Zhixiang / Zhou, Jinjia / Goto, Satoshi et al. | 2014
- 90
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Nano Magnetic STT-Logic Partitioning for Optimum PerformanceDas, Jayita / Alam, Syed M. / Bhanja, Sanjukta et al. | 2014
- 90
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Logic Families - Nano Magnetic STT-Logic Partitioning for Optimum PerformanceDas, J et al. | 2014
- 99
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Gate Mapping Automation for Asynchronous NULL Convention Logic CircuitsParsan, Farhad A. / Al-Assadi, Waleed K. / Smith, Scott C. et al. | 2014
- 113
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ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual ChannelsFu, Binzhang / Han, Yinhe / Li, Huawei / Li, Xiaowei et al. | 2014
- 113
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Fault Tolerant Design - ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual ChannelsFu, B et al. | 2014
- 127
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Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix CodeGuo, Jing / Xiao, Liyi / Mao, Zhigang / Zhao, Qiang et al. | 2014
- 136
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Power-Planning-Aware Soft Error Hardening via Selective Voltage AssignmentWu, Kai-Chiang / Marculescu, Diana et al. | 2014
- 146
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Interconnect Modeling and Design - Extraction of VLSI Multiconductor Transmission Line Parameters by ComplementaritySpecogna, R et al. | 2014
- 146
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Extraction of VLSI Multiconductor Transmission Line Parameters by ComplementaritySpecogna, Ruben et al. | 2014
- 155
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Exploring High-Throughput Computing Paradigm for Global RoutingHan, Yiding / Ancajas, Dean Michael / Chakraborty, Koushik / Roy, Sanghamitra et al. | 2014
- 168
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WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW ArchitectureHuang, Yazhi / Shi, Liang / Li, Jianhua / Li, Qingan / Xue, Chun Jason et al. | 2014
- 168
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Retiming - WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW ArchitectureHuang, Y et al. | 2014
- 181
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-ThroughLin, Jin-Fa et al. | 2014
- 181
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BRIEF PAPERS - Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through SchemeLin, J-F et al. | 2014
- 185
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Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture CachesBardine, Alessandro / Comparetti, Manuel / Foglia, Pierfrancesco / Prete, Cosimo Antonio et al. | 2014
- 185
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Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture CacheseBardine, A et al. | 2014
- 190
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Resistive Threshold LogicJames, Alex Pappachen / Francis, Linu Rose V. J. / Kumar, Dinesh S. et al. | 2014
- 196
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors| 2014
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Table of contents| 2014
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2014
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