A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation (English)
- New search for: Gornik, Andreas
- New search for: Gornik, Andreas
- New search for: Moradi, Amir
- New search for: Oehm, Jurgen
- New search for: Paar, Christof
In:
IEEE transactions on computer-aided design of integrated circuits and systems
;
34
, 8
; 1308-1319
;
2015
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ISSN:
- Article (Journal) / Print
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Title:A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation
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Contributors:
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Published in:IEEE transactions on computer-aided design of integrated circuits and systems ; 34, 8 ; 1308-1319
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2015
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ISSN:
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ZDBID:
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DOI:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 770/3155/5670
- New search for: 53.52 / 33.72 / 33.61 / 53.51
- Further information on Basic classification
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Keywords:
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Classification:
Local classification TIB: 770/3155/5670 BKL: 53.52 Elektronische Schaltungen / 33.72 Halbleiterphysik / 33.61 Festkörperphysik / 53.51 Bauelemente der Elektronik -
Source:
Table of contents – Volume 34, Issue 8
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1145
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MARS: Matching-Driven Analog SizingEick, M et al. | 2015
- 1159
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TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking SystemXiaoke Qin et al. | 2015
- 1169
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FIR filter synthesis based on interleaved processing of coefficient generation and multiplier-block synthesisByeong Yong Kong et al. | 2015
- 1180
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Time-domain analysis of large-scale circuits by matrix exponential method with adaptive controlQuan Chen et al. | 2015
- 1194
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TSV stress-aware full-chip mechanical reliability analysis and optimization for 3-D ICMoongon Jung et al. | 2015
- 1208
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An analytical placer for VLSI standard cell placementJianli Chen et al. | 2015
- 1209
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Real-Time Use-Aware Adaptive RF Transceiver Systems for Energy Efficiency Under BER ConstraintsBanerjee, Debashis / Devarakond, Shyam Kumar / Wang, Xian / Sen, Shreyas / Chatterjee, Abhijit et al. | 2015
- 1222
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Variation-aware clock network design methodology for Ultralow Voltage circuitsXin Zhao et al. | 2015
- 1223
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Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient AcceleratorsDu, Zidong / Lingamneni, Avinash / Chen, Yunji / Palem, Krishna V. / Temam, Olivier / Wu, Chengyong et al. | 2015
- 1235
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A dynamically adjusting gracefully degrading link-level fault-tolerant mechanism for NoCsVitkovskiy, A et al. | 2015
- 1236
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FPGA Trojans Through Detecting and Weakening of Cryptographic PrimitivesSwierczynski, Pawel / Fyrbiak, Marc / Koppe, Philipp / Paar, Christof et al. | 2015
- 1249
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Automatic TLM fault localization for systemcLe, H.M et al. | 2015
- 1250
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LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICsLee, Yu-Min / Pan, Chi-Wen / Huang, Pei-Yu / Yang, Chi-Ping et al. | 2015
- 1263
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On signal selection for visibility enhancement in trace-based post-silicon validationXiao Liu et al. | 2015
- 1264
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An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC ArchitecturesWu, Chen / Deng, Chenchen / Liu, Leibo / Han, Jie / Chen, Jiqiang / Yin, Shouyi / Wei, Shaojun et al. | 2015
- 1278
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LASIC: Layout Analysis for Systematic IC-Defect Identification Using ClusteringTam, Wing Chiu Jason / Blanton, Ronald D. Shawn et al. | 2015
- 1288
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Inferring assertion for complementary synthesisShengYu Shen et al. | 2015
- 1291
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Modeling STI Edge Parasitic Current for Accurate Circuit SimulationsKhandelwal, Sourabh / Agarwal, Harshit / Duarte, Juan Pablo / Chan, Kaiman / Dey, Sagnik / Chauhan, Yogesh Singh / Hu, Chenming et al. | 2015
- 1293
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A novel method for reducing metal variation with statistical static timing analysisForeman, E.A et al. | 2015
- 1295
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On the Pitfalls of Using Arbiter-PUFs as Building BlocksBecker, Georg T. et al. | 2015
- 1297
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Concurrent generation of concurrent programs for post-silicon validationAdir, A et al. | 2015
- 1308
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A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and EvaluationGornik, Andreas / Moradi, Amir / Oehm, Jurgen / Paar, Christof et al. | 2015
- 1320
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The MEET Approach: Securing Cryptographic Embedded Software Against Side Channel AttacksAgosta, Giovanni / Barenghi, Alessandro / Pelosi, Gerardo / Scandale, Michele et al. | 2015
- 1334
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A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning AttacksSahoo, Durga Prasad / Nguyen, Phuong Ha / Mukhopadhyay, Debdeep / Chakraborty, Rajat Subhra et al. | 2015
- 1344
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Security in MPSoCs: A NoC Firewall and an Evaluation FrameworkGrammatikakis, Miltos D. / Papadimitriou, Kyprianos / Petrakis, Polydoros / Papagrigoriou, Antonis / Kornaros, George / Christoforakis, Ioannis / Tomoutzoglou, Othon / Tsamis, George / Coppola, Marcello et al. | 2015
- 1358
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Formal Vulnerability Analysis of Security ComponentsFeiten, Linus / Sauer, Matthias / Schubert, Tobias / Tomashevich, Victor / Polian, Ilia / Becker, Bernd et al. | 2015
- 1370
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Call for keynote paper abstracts| 2015
- 1371
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Call for nominations for editor-in-chief of the IEEE design and test magazine| 2015
- 1372
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Open Access| 2015
- C1
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Table of contents| 2015
- C2
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information| 2015
- C3
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information| 2015
- C4
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors| 2015