Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs (English)
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In:
Applied Reconfigurable Computing. Architectures, Tools, and Applications
: 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings
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Chapter: 11
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136-150
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2020
- Article/Chapter (Book) / Electronic Resource
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Title:Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs
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Additional title:Lect.Notes Computer
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Contributors:Rincón, Fernando ( editor ) / Barba, Jesús ( editor ) / So, Hayden K. H. ( editor ) / Diniz, Pedro ( editor ) / Caba, Julián ( editor ) / Suriano, Leonardo ( author ) / Lima, David ( author ) / de la Torre, Eduardo ( author )
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Conference:International Symposium on Applied Reconfigurable Computing ; 2020 ; Toledo, Spain
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Published in:Applied Reconfigurable Computing. Architectures, Tools, and Applications : 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings ; Chapter: 11 ; 136-150Lecture Notes in Computer Science ; 12083 ; 136-150
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Publisher:
- New search for: Springer International Publishing
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Place of publication:Cham
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Publication date:2020-03-25
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Size:15 pages
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ISBN:
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ISSN:
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DOI:
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Type of media:Article/Chapter (Book)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents eBook
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural NetworksFerianc, Martin / Fan, Hongxiang / Chu, Ringo S. W. / Stano, Jakub / Luk, Wayne et al. | 2020
- 2
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Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware DesignAnsaloni, Giovanni / Scarabottolo, Ilaria / Pozzi, Laura et al. | 2020
- 3
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Optimising Operator Sets for Analytical Database Processing on FPGAsDrewes, Anna / Joseph, Jan Moritz / Gurumurthy, Bala / Broneske, David / Saake, Gunter / Pionteck, Thilo et al. | 2020
- 4
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Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator SystemsOrtiz, Alberto / Zamacola, Rafael / Rodríguez, Alfonso / Otero, Andrés / de la Torre, Eduardo et al. | 2020
- 5
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Chisel Usecase: Designing General Matrix Multiply for FPGAFerres, Bruno / Muller, Olivier / Rousseau, Frédéric et al. | 2020
- 6
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Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural NetworksKhan, Habib ul Hasan / Podlubne, Ariel / Akgün, Gökhan / Göhringer, Diana et al. | 2020
- 7
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Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAsBozzoli, Ludovica / Sterpone, Luca et al. | 2020
- 8
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SysIDLib: A High-Level Synthesis FPGA Library for Online System IdentificationAkgün, Gökhan / Khan, Habib ul Hasan / Hebaish, Marawan / Elshimy, Mahmoud / Ghany, Mohamed A. Abd El / Göhringer, Diana et al. | 2020
- 9
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Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing DevicesGuettatfi, Zakarya / Kaufmann, Paul / Platzner, Marco et al. | 2020
- 10
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Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAsBacchus, Pascal / Stewart, Robert / Komendantskaya, Ekaterina et al. | 2020
- 11
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Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCsSuriano, Leonardo / Lima, David / de la Torre, Eduardo et al. | 2020
- 12
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Cross-layer CNN Approximations for Hardware ImplementationAli, Karim M. A. / Alouani, Ihsen / El Cadi, Abdessamad Ait / Ouarnoughi, Hamza / Niar, Smail et al. | 2020
- 13
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Technique for Vendor and Device Agnostic Hardware Area-Time EstimationWijesundera, Deshya / Shah, Kushagra / Liyanage, Kisaru / Prakash, Alok / Srikanthan, Thambipillai / Perera, Thilina et al. | 2020
- 14
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Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAsAkgün, Gökhan / Kalms, Lester / Göhringer, Diana et al. | 2020
- 15
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RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and PerformanceAli, Muhammad / Amini Rad, Pedram / Göhringer, Diana et al. | 2020
- 16
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A Modular Software Library for Effective High Level Synthesis of Convolutional Neural NetworksHernandez, Hector Gerardo Munoz / Mahmood, Safdar / Brandalero, Marcelo / Hübner, Michael et al. | 2020
- 17
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HLS-Based Acceleration Framework for Deep Convolutional Neural NetworksMisra, Ashish / Kindratenko, Volodymyr et al. | 2020
- 18
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FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design MethodDu, Changdao / Firmansyah, Iman / Yamaguchi, Yoshiki et al. | 2020
- 19
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High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware CodesignNguyen, Duc Tri / Dang, Viet B. / Gaj, Kris et al. | 2020
- 20
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Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra KernelsFavaro, Federico / Dufrechou, Ernesto / Ezzatti, Pablo / Oliver, Juan P. et al. | 2020
- 21
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A CGRA Definition Framework for Dataflow ApplicationsCharitopoulos, George / Pnevmatikatos, Dionisios N. et al. | 2020
- 22
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Implementing CNNs Using a Linear Array of Full Mesh CGRAsMário, Valter / Lopes, João D. / Véstias, Mário / de Sousa, José T. et al. | 2020
- 23
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A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence AlignmentBen Abdelhamid, Riadh / Yamaguchi, Yoshiki et al. | 2020
- 24
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Comparison of Direct and Indirect Networks for High-Performance FPGA ClustersMondigo, Antoniette / Ueno, Tomohiro / Sano, Kentaro / Takizawa, Hiroyuki et al. | 2020
- 25
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A Parameterisable FPGA-Tailored Architecture for YOLOv3-TinyYu, Zhewen / Bouganis, Christos-Savvas et al. | 2020
- 26
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Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAsIkeda, Taiga / Sakurada, Kento / Nakamura, Atsuyoshi / Motomura, Masato / Takamaeda-Yamazaki, Shinya et al. | 2020
- 27
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StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip ArchitecturesZhanbolatov, Arshyn / Vipin, Kizheppatt / Dadlani, Aresh / Fedorov, Dmitriy et al. | 2020
- 28
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Implementation of FM-Index Based Pattern Search on a Multi-FPGA SystemUllah, M. M. Imdad / Ben Ahmed, Akram / Amano, Hideharu et al. | 2020
- 29
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Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection AlgorithmDuarte, Rui P. / Cruz, Helena / Neto, Horácio et al. | 2020
- 30
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Correction to: Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection AlgorithmDuarte, Rui P. / Cruz, Helena / Neto, Horácio et al. | 2020