A case study of partially evaluated hardware circuits: Key-specific DES (English)
- New search for: Leonard, Jason
- New search for: Mangione-Smith, William H.
- New search for: Leonard, Jason
- New search for: Mangione-Smith, William H.
In:
Field-Programmable Logic and Applications
;
151-160
;
1997
- Article/Chapter (Book) / Electronic Resource
-
Title:A case study of partially evaluated hardware circuits: Key-specific DES
-
Contributors:Leonard, Jason ( author ) / Mangione-Smith, William H. ( author )
-
Published in:Lecture Notes in Computer Science ; 1304 ; 151-160
-
Publisher:
- New search for: Springer Berlin Heidelberg
-
Place of publication:Berlin, Heidelberg
-
Publication date:1997-01-01
-
Size:10 pages
-
ISBN:
-
ISSN:
-
DOI:
-
Type of media:Article/Chapter (Book)
-
Type of material:Electronic Resource
-
Language:English
-
Keywords:
-
Source:
Table of contents eBook
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
-
Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessorFaura, Julio / Moreno, Juan Manuel / Aguirre, Miguel Angel / Duong, Phuoc / Insenser, Josep Maria et al. | 1997
- 11
-
CAD-oriented FPGA and dedicated CAD system for telecommunicationsMiyazaki, Toshiaki / Takahara, Atsushi / Katayama, Masaru / Murooka, Takahiro / Ichimorit, Takaki / Fukamitt, Kennosuke / Tsutsuittt, Akihiro / Hayashittt, Kazuhiro et al. | 1997
- 21
-
Rothko: A three dimensional FPGA architecture, its fabrication, and design toolsLeeser, Miriam / Meleis, Waleed M. / Vai, Mankuan M. / Zavracky, Paul et al. | 1997
- 31
-
Extending dynamic circuit switching to meet the challenges of new FPGA architecturesMcGregor, Gordon / Lysaght, Patrick et al. | 1997
- 41
-
Performance evaluation of a full speed PCI initiator and target subsystem using FPGAsRobinson, David / Lysaght, Patrick / McGregor, Gordon / Dick, Hugh et al. | 1997
- 51
-
Implementation of pipelined multipliers on Xilinx FPGAsDo, T. -T. / Kropp, H. / Schwiegershausen, M. / Pirsch, P. et al. | 1997
- 61
-
The XC620ODS development systemNisbet, Stuart / Guccione, Steven A. et al. | 1997
- 69
-
Thermal monitoring on FPGAs using ring-oscillatorsBoemo, Eduardo / López-Buedo, Sergio et al. | 1997
- 79
-
A reconfigurable approach to low cost media processingKostarnov, Igor / Morley, Steve / Osmany, Javed / Solomon, Charlie et al. | 1997
- 91
-
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing researchMackinlay, Patrick I. / Cheung, Peter Y. K. / Luk, Wayne / Sandiford, Richard et al. | 1997
- 101
-
Stream synthesis for a wormhole run-time reconfigurable platformKahne, Brian / Athanas, Peter et al. | 1997
- 111
-
Pipeline morphing and virtual pipelinesLuk, W. / Shirazi, N. / Guo, S. R. / Cheung, P. Y. K. et al. | 1997
- 121
-
Parallel graph colouring using FPGAsRising, Barry / Daalen, Max / Burge, Peter / Shawe-Taylor, John et al. | 1997
- 131
-
Run-time compaction of FPGA designsDiessel, Oliver / ElGindy, Hossam et al. | 1997
- 141
-
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancementEmmert, John M. / Bhatia, Dinesh et al. | 1997
- 151
-
A case study of partially evaluated hardware circuits: Key-specific DESLeonard, Jason / Mangione-Smith, William H. et al. | 1997
- 161
-
Run-time parameterised circuits for the Xilinx XC6200Payne, Rob et al. | 1997
- 173
-
Automatic identification of swappable logic units in XC6200 circuitryBrebner, Gordon et al. | 1997
- 183
-
Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logicLysaght, Patrick et al. | 1997
- 193
-
Exploiting reconfigurability through domain-specific systemsHutchings, Brad L. et al. | 1997
- 203
-
Technology mapping by binate coveringServít, Michal Z. / YI, Kang et al. | 1997
- 213
-
VPR: a new packing, placement and routing tool for FPGA researchBetz, Vaughn / Rose, Jonathan et al. | 1997
- 223
-
Technology mapping of heterogeneous LUT-based FPGAsInuani, Maurice Kilavuka / Saul, Jonathan et al. | 1997
- 235
-
Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAsFeske, Klaus / Mulka, Sven / Koegst, Manfred / Elst, Günte et al. | 1997
- 245
-
Technology mapping of LUT based FPGAs for delay optimisationLin, Xiaochun / Dagless, Erik / Lu, Aiguo et al. | 1997
- 255
-
Automatic Mapping of Algorithms onto multiple FPGA-SRAM ModulesAcock, S.J.B. / Dimond, K.R. et al. | 1997
- 265
-
FPLD HDL synthesis employing high-level evolutionary algorithm optimisationMaunder, R.Bruce / Salcic, Zoran A. / Coghill, George G. et al. | 1997
- 274
-
An hardware/software partitioning algorithm for custom computing machinesChichkov, Anton / Almeida, Carlos et al. | 1997
- 284
-
The Java Environment for Reconfigurable ComputingLechner, Eric / Guccione, Steven A. et al. | 1997
- 294
-
Data scheduling to increase performance of parallel acceleratorsHartenstein, R. W. / Becker, J. / Herz, M. / Nageldinger, U. et al. | 1997
- 304
-
An operating system for custom computing machines based on the Xputer paradigmKress, Rainer / Hartenstein, Reiner W. / Nageldinger, Ulrich et al. | 1997
- 314
-
Fast parallel implementation of DFT using configurable devicesDandalis, Andreas / Prasanna, Viktor K. et al. | 1997
- 324
-
Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elementsGreenfield, David / Crome, Caleb / Won, Martin S. / Amos, Doug et al. | 1997
- 333
-
A case study of algorithm implementation in reconfigurable hardware and softwareShand, Mark et al. | 1997
- 344
-
A reconfigurable data-localised array for morphological algorithmsChaudhuri, Anjit Sekhar / Cheung, Peter Y. K. / Luk, Wayne et al. | 1997
- 354
-
Virtual radix array processors (V-RaAP)Bramer, B. / Chauhan, D. / Ibrahim, M. K. / Aggoun, A. et al. | 1997
- 364
-
An FPGA implementation of a matched filter detector for spread spectrum communications systemsMathews, T. / Gibb, S. G. / Turner, L. E. / Graumann, P. J. W. / Fattouche, M. et al. | 1997
- 374
-
An NTSC and PAL closed caption processorTeerapanyawatt, Sayan / Athikulwongse, Krit et al. | 1997
- 382
-
A 800Mpixel/sec reconfigurable image correlator on XC6216Kean, Tom / Duncan, Ann et al. | 1997
- 392
-
A reconfigurable coprocessor for a PCI-based real time computer vision systemLisa, Ferran / Cuadrado, Faustino / Rexachs, Dolores / Carrabina, Jordi et al. | 1997
- 400
-
Real-time stereopsis using FPGAsDunn, Paul / Corke, Peter et al. | 1997
- 410
-
FPGAs Implementation of a digital IQ demodulator using VHDLJong, C. C. / Lam, Y. Y. H. / Ng, L. S. et al. | 1997
- 418
-
Hardware compilation, configurable platforms and ASICs for self-validating sensorsPage, Ian et al. | 1997
- 428
-
PostScript™ rendering with virtual hardwareSingh, Satnam / Patterson, John / Burns, Jim / Dales, Michael et al. | 1997
- 438
-
P4: A platform for FPGA implementation of protocol boostersHadžić, Ilija / Smith, Jonathan M. et al. | 1997
- 448
-
Satisfiability on reconfigurable hardwareAbramovici, Miron / Saab, Daniel et al. | 1997
- 457
-
Auto-configurable array for GCD computationJebelean, Tudor et al. | 1997
- 462
-
Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGALaurent, B. / Bosco, G. / Saucier, G. et al. | 1997
- 472
-
FPGA implementation of real-time digital controllers using on-line arithmeticTisserand, Arnaud / Dimmler, Martin et al. | 1997
- 482
-
A prototyping environment for fuzzy controllersHollstein, Thomas / Kirschbaum, Andreas / Glesner, Manfred et al. | 1997
- 491
-
A reconfigurable sensor-data processing system for personal robotsNukata, Kazumasa / Shibata, Yuichiro / Amano, Hideharu / Anzai, Yuichiro et al. | 1997