Register-Transfer Level Correspondence Analysis (English)
- New search for: Herdt, Vladimir
- New search for: Große, Daniel
- New search for: Drechsler, Rolf
- New search for: Herdt, Vladimir
- New search for: Große, Daniel
- New search for: Drechsler, Rolf
In:
Enhanced Virtual Prototyping
: Featuring RISC-V Case Studies
;
Chapter: 8
;
205-229
;
2020
- Article/Chapter (Book) / Electronic Resource
-
Title:Register-Transfer Level Correspondence Analysis
-
Contributors:
-
Published in:Enhanced Virtual Prototyping : Featuring RISC-V Case Studies ; Chapter: 8 ; 205-229
-
Publisher:
- New search for: Springer International Publishing
-
Place of publication:Cham
-
Publication date:2020-10-15
-
Size:25 pages
-
ISBN:
-
DOI:
-
Type of media:Article/Chapter (Book)
-
Type of material:Electronic Resource
-
Language:English
-
Keywords:Virtual prototype (VP) , SystemC , Register-transfer level (RTL) , Transaction level modeling (TLM) , Correspondence analysis , Property checking , Property refinement , Fault correspondence , Fault injection , Fault localization , Symbolic simulation , Symbolic execution , Formal methods , Formal specification , Error effect simulation , Cross-level , Transactor , Co-simulation , Static analysis , Bit flip , SoCRocket , Symbolic error injection
-
Source:
Table of contents eBook
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
-
IntroductionHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 2
-
PreliminariesHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 3
-
An Open-Source RISC-V Evaluation PlatformHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 4
-
Formal Verification of SystemC-Based Designs using Symbolic SimulationHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 5
-
Coverage-Guided Testing for Scalable Virtual Prototype VerificationHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 6
-
Verification of Embedded Software Binaries using Virtual PrototypesHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 7
-
Validation of Firmware-Based Power Management using Virtual PrototypesHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 8
-
Register-Transfer Level Correspondence AnalysisHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020
- 9
-
ConclusionHerdt, Vladimir / Große, Daniel / Drechsler, Rolf et al. | 2020