XEEMU: An Improved XScale Power Simulator (English)
- New search for: Herczeg, Zoltán
- New search for: Kiss, Ákos
- New search for: Schmidt, Daniel
- New search for: Wehn, Norbert
- New search for: Gyimóthy, Tibor
- New search for: Herczeg, Zoltán
- New search for: Kiss, Ákos
- New search for: Schmidt, Daniel
- New search for: Wehn, Norbert
- New search for: Gyimóthy, Tibor
In:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
7
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300-309
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2007
- Article/Chapter (Book) / Electronic Resource
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Title:XEEMU: An Improved XScale Power Simulator
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Contributors:Herczeg, Zoltán ( author ) / Kiss, Ákos ( author ) / Schmidt, Daniel ( author ) / Wehn, Norbert ( author ) / Gyimóthy, Tibor ( author )
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Published in:Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation , 7 ; 300-309Lecture Notes in Computer Science ; 4644, 7 ; 300-309
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Publisher:
- New search for: Springer Berlin Heidelberg
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Place of publication:Berlin, Heidelberg
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Publication date:2007-01-01
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Size:10 pages
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ISBN:
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ISSN:
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DOI:
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Type of media:Article/Chapter (Book)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents eBook
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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System-Level Application-Specific NoC Design for Network and Multimedia ApplicationsPapadopoulos, Lazaros / Soudris, Dimitrios et al. | 2007
- 10
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Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive MeasurementsFournel, Nicolas / Fraboulet, Antoine / Feautrier, Paul et al. | 2007
- 20
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A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable PlatformsPanagopoulos, Ioannis / Pavlatos, Christos / Manis, George / Papakonstantinou, George et al. | 2007
- 31
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An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC ArchitectureDelorme, Julien et al. | 2007
- 43
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Template Vertical Dictionary-Based Program Compression Scheme on the TTAMingche, Lai / Zhiying, Wang / JianJun, Guo / Kui, Dai / Li, Shen et al. | 2007
- 53
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Asynchronous Functional Coupling for Low Power Sensor Network ProcessorsShang, Delong / Shin, Chihoon / Wang, Ping / Xia, Fei / Koelmans, Albert / Oh, Myeonghoon / Kim, Seongwoon / Yakovlev, Alex et al. | 2007
- 64
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A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential DesignsChabini, Noureddine et al. | 2007
- 75
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Low-Power Content Addressable Memory With Read/Write and Matched Mask PortsAbdel-Hafeez, Saleh / Harb, Shadi M. / Eisenstadt, William R. et al. | 2007
- 86
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The Design and Implementation of a Power Efficient Embedded SRAMLiu, Yijun / Chen, Pinghua / Wang, Wenyan / Li, Zhenkun et al. | 2007
- 97
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Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADINLipka, Björn / Kleine, Ulrich et al. | 2007
- 107
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Settling Time Minimization of Operational AmplifiersPugliese, Andrea / Cappuccino, Gregorio / Cocorullo, Giuseppe et al. | 2007
- 117
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Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTsPopa, Cosmin et al. | 2007
- 125
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Computation of Joint Timing Yield of Sequential Networks Considering Process VariationsGoel, Amit / Bhardwaj, Sarvesh / Ghanta, Praveen / Vrudhula, Sarma et al. | 2007
- 138
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A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin EvaluationMigairou, V. / Wilson, R. / Engels, S. / Wu, Z. / Azemard, N. / Maurine, P. et al. | 2007
- 148
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A Statistical Approach to the Timing-Yield Optimization of Pipeline CircuitsHsu, Chin-Hsiung / Chou, Szu-Jui / Jiang, Jie-Hong R. / Chang, Yao-Wen et al. | 2007
- 160
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A Novel Gate-Level NBTI Delay Degradation Model with Stacking EffectLuo, Hong / Wang, Yu / He, Ku / Luo, Rong / Yang, Huazhong / Xie, Yuan et al. | 2007
- 171
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Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-ComponentsHoyer, Marko / Helms, Domenik / Nebel, Wolfgang et al. | 2007
- 181
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Logic Style Comparison for Ultra Low Power Operation in 65nm TechnologySingh, Mandeep / Giacomotto, Christophe / Zeydel, Bart / Oklobdzija, Vojin et al. | 2007
- 191
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Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI DegradationParthasarathy, CR. / Bravaix, A. / Guérin, C. / Denais, M. / Huard, V. et al. | 2007
- 201
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Clock Distribution Techniques for Low-EMI DesignPandini, Davide / Repetto, Guido A. / Sinisi, Vincenzo et al. | 2007
- 211
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Crosstalk Waveform Modeling Using Wave FittingNanua, Mini / Blaauw, David et al. | 2007
- 222
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Weakness Identification for Effective Repair of Power Distribution NetworkSato, Takashi / Hagiwara, Shiho / Uezono, Takumi / Masu, Kazuya et al. | 2007
- 232
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New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip BusesSithambaram, P. / Macii, A. / Macii, E. et al. | 2007
- 242
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On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron InterconnectsMurgan, T. / Bacinschi, P. B. / Pandey, S. / Ortiz, A. García / Glesner, M. et al. | 2007
- 255
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Soft Error-Aware Power Optimization Using Gate SizingDabiri, Foad / Nahapetian, Ani / Potkonjak, Miodrag / Sarrafzadeh, Majid et al. | 2007
- 268
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Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile DevicesGrumer, Matthias / Wendt, Manuel / Steger, Christian / Weiss, Reinhold / Neffe, Ulrich / Mühlberger, Andreas et al. | 2007
- 278
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RTL Power Modeling and Estimation of Sleep Transistor Based Power GatingRosinger, Sven / Helms, Domenik / Nebel, Wolfgang et al. | 2007
- 288
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Functional Verification of Low Power Designs at RTLCrone, Allan / Chidolue, Gabriel et al. | 2007
- 300
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XEEMU: An Improved XScale Power SimulatorHerczeg, Zoltán / Kiss, Ákos / Schmidt, Daniel / Wehn, Norbert / Gyimóthy, Tibor et al. | 2007
- 310
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Low Power Elliptic Curve CryptographyKeller, Maurice / Marnane, William et al. | 2007
- 320
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Design and Test of Self-checking Asynchronous Control CircuitRuan, Jian / Wang, Zhiying / Dai, Kui / Li, Yong et al. | 2007
- 330
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An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-ChipsGhavami, Behnam / Pedram, Hossein et al. | 2007
- 340
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPARazafindraibe, A. / Robert, M. / Maurine, P. et al. | 2007
- 352
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Performance Optimization of Embedded Applications in a Hybrid Reconfigurable PlatformGalanis, Michalis D. / Dimitroulakos, Gregory / Goutis, Costas E. et al. | 2007
- 363
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The Energy Scalability of Wavelet-Based, Scalable Video DecodingEeckhaut, Hendrik / Devos, Harald / Stroobandt, Dirk et al. | 2007
- 373
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Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy ConsumptionPeon-Quiros, Miguel / Bartzas, Alexandros / Mamagkakis, Stylianos / Catthoor, Francky / Mendias, Jose M. / Soudris, Dimitrios et al. | 2007
- 384
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Exploiting Input Variations for Energy ReductionSato, Toshinori / Kunitake, Yuji et al. | 2007
- 394
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A Model of DPA Syndrome and Its Application to the Identification of Leaking GatesRazafindraibe, A. / Maurine, P. et al. | 2007
- 404
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Static Power Consumption in CMOS Gates Using Independent BodiesGuerrero, D. / Millan, A. / Juan, J. / Bellido, M. J. / Ruiz-de-Clavijo, P. / Ostua, E. / Viejo, J. et al. | 2007
- 413
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Moderate Inversion: Highlights for Low Voltage DesignGuigues, Fabrice / Kussener, Edith / Duval, Benjamin / Barthelemy, Hervé et al. | 2007
- 423
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On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time SystemsKamiura, Naotake / Isokawa, Teijiro / Matsui, Nobuyuki et al. | 2007
- 433
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Semi Custom Design: A Case Study on SIMD ShufflersRaghavan, Praveen / Sethubalasubramanian, Nandhavel / Munaga, Satyakiran / Ramos, Estela Rey / Jayapala, Murali / Weiss, Oliver / Catthoor, Francky / Verkest, Diederik et al. | 2007
- 443
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Optimization for Real-Time Systems with Non-convex Power Versus Speed ModelsNahapetian, Ani / Dabiri, Foad / Potkonjak, Miodrag / Sarrafzadeh, Majid et al. | 2007
- 453
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Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOSChen, Harry I. A. / Loo, Edward K. W. / Kuo, James B. / Syrzycki, Marek J. et al. | 2007
- 463
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A Fast and Accurate Power Estimation Methodology for QDI Asynchronous CircuitsGhavami, Behnam / Niknahad, Mahtab / Najibi, Mehrdad / Pedram, Hossein et al. | 2007
- 474
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Subthreshold Leakage Modeling and Estimation of General CMOS Complex GatesButzen, Paulo F. / Reis, André I. / Kim, Chris H. / Ribas, Renato P. et al. | 2007
- 485
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A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW PartitioningLucarz, Christophe / Mattavelli, Marco et al. | 2007
- 495
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Fast Calculation of Permissible Slowdown Factors for Hard Real-Time SystemsLipskoch, Henrik / Albers, Karsten / Slomka, Frank et al. | 2007
- 505
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Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss RateKroupis, N. / Soudris, D. et al. | 2007
- 516
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A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip VariationsCenturelli, Francesco / Giancane, Luca / Olivieri, Mauro / Scotti, Giuseppe / Trifiletti, Alessandro et al. | 2007
- 526
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Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input DataGustafson, Oscar / Oskuii, Saeeid Tahmasbi / Johansson, Kenny / Kjeldsberg, Per Gunnar et al. | 2007
- 536
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Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power SupplyAlfredsson, Jon / Aunet, Snorre et al. | 2007
- 546
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Low-Power Digital Filtering Based on the Logarithmic Number SystemBasetas, Ch. / Kouretas, I. / Paliouras, V. et al. | 2007
- 556
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A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage ScalingMiermont, Sylvain / Vivet, Pascal / Renaudin, Marc et al. | 2007
- 566
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Dependability Evaluation of Time-Redundancy Techniques in Integer MultipliersEriksson, Henrik et al. | 2007
- 576
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Design and Industrialization Challenges of Memory Dominated SOCsDaga, J. M. et al. | 2007
- 577
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Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer TechnologiesPandini, D. et al. | 2007
- 578
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Analog Power ModellingSvensson, C. et al. | 2007
- 579
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Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone PlatformsDahlgren, F. et al. | 2007
- 580
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System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving ParametersEmrich, A. et al. | 2007