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For the first time from the beginning of microelectronics, the device scaling down could encounter serious physical and technological limits that the conventional bulk MOSFET probably will be notable to overcome beyond 2008-2010. This paper review the problems related to the MOS transistor scaling and the intrinsic limitations associated to the bulk architecture. The authors present the key physical phenomena governing the operation of advanced devices, at the decanenometric scale (nonstationary phenomena, ballistic transport, quantum effects, parameter fluctuations).In a second part, the authors examine different innovative MOS architectures at the state-of-the-art (MOS transistor with strained silicon channel, SOI and SON transistors, double- gate, GAA and FinFET architectures) which are candidate to replace the conventional bulk MOSFET beyond the 45 nm generation. Several exploratory solutions are finally presented for 'the after roadmap'.
Les architectures innovantes sur silicium mince. Un second souffle pour la loi de Moore?
Additional title:
Innovative Architekturen von Dünnschicht-FET. Eine Fortschreibung des Gesetzes von Moore?
Innovative architectures on thin silicon. Second lease of life for Moore's law?