Time domain numerical simulation for transient waves on reconfigurable coprocessor platform (English)
- New search for: He, C.
- New search for: Zhao, W.
- New search for: Lu, M.
- New search for: He, C.
- New search for: Zhao, W.
- New search for: Lu, M.
In:
Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 13
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127-136
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2005
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ISBN:
- Conference paper / Print
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Title:Time domain numerical simulation for transient waves on reconfigurable coprocessor platform
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE Computer Society Press
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Place of publication:Los Alamitos
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Publication date:2005
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Size:10 Seiten, 15 Quellen
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ISBN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
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Efficient hardware data mining with the Apriori algorithm on FPGAsBaker, Z.K. / Prasanna, V.K. et al. | 2005
- 13
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A novel 2D filter design methodology for heterogeneous devicesBouganis, C.-S. / Constantinides, G.A. / Cheung, P.Y.K. et al. | 2005
- 23
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Prototyping architectural support for program rollback using FPGAsTeodorescu, R. / Torrellas, J. et al. | 2005
- 35
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Register file architecture optimization in a coarse-grained reconfigurable architectureKwok, Z. / Wilton, S.J.E. et al. | 2005
- 45
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Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chipLertora, F. / Borgatti, M. et al. | 2005
- 57
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A study of the scalability of on-chip routing for just-in-time FPGA compilationLysecky, R. / Vahid, F. / Tan, S.D.-X. et al. | 2005
- 63
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Simplifying the integration of processing elements in computing systems using a programmable controllerShannon, L. / Chow, P. et al. | 2005
- 73
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Evaluation of code generation strategies for scalar replaced codes in fine-grain configurable architecturesDiniz, P.C. et al. | 2005
- 85
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FPGA particle graphics hardwareBeeckler, J.S. / Gross, W.J. et al. | 2005
- 95
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Reconfigurable designs for radiosityBaker, P. / Todman, T. / Styles, H. / Luk, W. et al. | 2005
- 107
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Hardware factorization based on elliptic curve methodSimka, M. / Pelzl, J. / Kleinjung, T. / Franke, J. / Priplata, C. / Stahlke, C. / Drutarovsky, M. / Fischer, V. / Paar, C. et al. | 2005
- 117
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Metropolitan road traffic simulation on FPGAsTripp, J.L. / Mortveit, H.S. / Hansson, A.A. / Gokhale, M. et al. | 2005
- 127
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Time domain numerical simulation for transient waves on reconfigurable coprocessor platformHe, C. / Zhao, W. / Lu, M. et al. | 2005
- 139
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COMA: a cooperative management scheme for energy efficient implementation of real-time operating systems on FPGA based soft processorsOu, J. / Prasanna, V.K. et al. | 2005
- 149
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An execution environment for reconfigurable computingFu, W. / Compton, K. et al. | 2005
- 161
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Higher radix floating-point representations for FPGA-based arithmeticCatanzaro, B. / Nelson, B. et al. | 2005
- 171
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An analysis of the double-precision floating-point FFT on FPGAsHemmert, K.S. / Underwood, K.D. et al. | 2005
- 181
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A comparison of floating point and logarithmic number systems for FPGAsHaselman, M. / Beauchamp, M. / Wood, A. / Hauck, S. / Underwood, K. / Hemmert, K.S. et al. | 2005
- 193
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Terrestrial-based radiation upsets: a cautionary taleQuinn, H. / Graham, P. et al. | 2005
- 203
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Automating the layout of reconfigurable subsystems using circuit generatorsPhillips, S. / Hauck, S. et al. | 2005
- 215
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Fast reconfiguring deep packet filter for 1+ gigabit networkCho, Y.H. / Mangione-Smith, W.H. et al. | 2005
- 225
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A framework for rule processing in reconfigurable network systemsAttig, M. / Lockwood, J. et al. | 2005
- 235
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A signature match processor architecture for network intrusion detectionJanardhan Singaraju, / Bu, L. / Chandy, J.A. et al. | 2005
- 245
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Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilationCoutinho, J.G.F. / Jiang, J. / Luk, W. et al. | 2005
- 255
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Modeling and FPGA implementation of applications using parameterized process networks with non-static parametersNikolov, H. / Stefanov, T. / Deprettere, E. et al. | 2005
- 267
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A BIST approach for testing FPGAs using JBITSNiamat, M.Y. / Hejeebu, S.S. / Alam, M. et al. | 2005
- 269
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Preliminary report: FPGA acceleration of molecular dynamics computationsGu, Y. / Van Court, T. / DiSabello, D. / Herbordt, M.C. et al. | 2005
- 271
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A high-performance asynchronous FPGA: test resultsFang, D. / Teifel, J. / Rajit Manohar, et al. | 2005
- 273
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Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architecturesBanerjee, S. / Bozorgzadeh, E. / Dutt, N. et al. | 2005
- 273
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RAVIOLI - reconfigurable arithmetic variable-precision implementations of on-line instructionsMcIlhenny, R. / Ercegovac, M.D. et al. | 2005
- 277
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FIFO communication models in operating systems for reconfigurable computingWilliams, J.A. / Bergmann, N.W. / Xie, X. et al. | 2005
- 279
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Astrophysical hydrodynamics simulations on a reconfigurable systemNakasato, N. / Hamada, T. et al. | 2005
- 281
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Post synthesis level power modeling of FPGAsFrench, M. / Wang, L. / Anderson, T. / Wirthlin, M. et al. | 2005
- 283
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FPGA-based CDMA switch for networks-on-chipKim, D. / Kim, M. / Sobelman, G.E. et al. | 2005
- 285
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Design of networked reconfigurable encryption engineFernando, S. / Yajun, H. et al. | 2005
- 287
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A virtual machine for merit-based runtime reconfigurationGreskamp, B. / Sass, R. et al. | 2005
- 289
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Automatic creation of domain-specific reconfigurable CPLDs for SoCHolland, M. / Hauck, S. et al. | 2005
- 291
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The GAPLA: a globally asynchronous locally synchronous FPGA architectureJia, X. / Vemuri, R. et al. | 2005
- 293
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Optimizing technology mapping for FPGAs using CAMsLucas, J.M. / Hoare, R. / Jones, A.K. et al. | 2005
- 295
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An architecture for video compression based on the SCAN algorithmSofikitis, H. / Roumpou, K. / Dollas, A. / Bourbakis, N. et al. | 2005
- 297
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An open TCP/IP core for reconfigurable logicDollas, A. / Ermis, I. / Koidis, I. / Zisis, I. / Kachris, C. et al. | 2005
- 299
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Mutable codesign for embedded protocol processingSproull, T. / Brebner, G. / Neely, C. et al. | 2005
- 301
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Accelerating applications by mapping critical kernels on coarse-grain reconfigurable hardware in hybrid systemsGalanis, M.D. / Dimitroulakos, G. / Goutis, C.E. et al. | 2005
- 303
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An embedded reconfigurable datapath for SoCLodi, A. / Ciccarelli, L. / Mucci, C. / Giansante, R. / Cappelli, A. et al. | 2005
- 305
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Systolic architecture for computing the discrete Fourier transform on FPGAsNash, J.G. et al. | 2005
- 307
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Hardware solution to Java compressed heapKato, M. / Lo, C.-T.D. et al. | 2005
- 309
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A general purpose, highly efficient communication controller architecture for hardware acceleration platformsCurt, P.F. / Durbano, J.P. / Ortiz, F.E. / Humphrey, J.R. / Prather, D.W. et al. | 2005
- 311
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Parallel hardware implementation of cellular learning automata based evolutionary computing (CLA-EC) on FPGAHariri, A. / Rastegar, R. / Zamani, M.S. / Meybodi, M.R. et al. | 2005
- 315
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Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processorAmano, H. / Abe, S. / Hasegawa, Y. / Deguchi, K. / Suzuki, M. et al. | 2005
- 317
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A system-on-programmable chip approach for MIMO sphere decoderJing Ma, / Xinming Huang, et al. | 2005
- 319
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The Erlangen Slot Machine: a highly flexible FPGA-based reconfigurable platformBobda, C. / Majer, M. / Ahmadinia, A. / Haller, T. / Linarth, A. / Teich, J. et al. | 2005
- 321
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Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platformsDonato, A. / Ferrandi, F. / Redaelli, M. / Santambrogio, M.D. / Sciuto, D. et al. | 2005
- 323
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High-performance FPGA-based general reduction methodsMorris, G.R. / Zhuo, L. / Prasanna, V.K. et al. | 2005
- 325
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Core-based methodology: an automated approach for implementing a complete system from algorithms to a heterogeneous network including FPGAsLam, J. / McAllister, J. / Dudley, J. et al. | 2005
- 327
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The DARPA dynamic programming benchmark on a reconfigurable computerCordova, L.E. / Buell, D.A. / Akella, S. et al. | 2005
- 329
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Massively parallel processors generator for reconfigurable systemHamada, T. / Nakasato, N. et al. | 2005
- 331
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FPGA-based vector processing for solving sparse sets of equationsHasan, M.Z. / Ziavras, S.G. et al. | 2005
- 333
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Exploiting multi-grained parallelism in reconfigurable SBC architecturesZambreno, J. / Dan Honbo, / Choudhary, A. et al. | 2005
- 335
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On distributed reconfigurable systems: open problems and some initial solutionsDollas, A. / Efstathiou, D. / Vernardos, G. / Polytarchos, E. / Kazakos, K. et al. | 2005
- 337
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Author index| 2005
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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Cover| 2005
- i
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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Title Page| 2005
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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Copyright Page| 2005
- v
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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Table of Contents| 2005
- xi
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Conference Organizers| 2005