0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM (English)
- New search for: Nakata, Yohei
- New search for: Okumura, Shunsuke
- New search for: Kawaguchi, Hiroshi
- New search for: Yoshimoto, Masahiko
- New search for: Nakata, Yohei
- New search for: Okumura, Shunsuke
- New search for: Kawaguchi, Hiroshi
- New search for: Yoshimoto, Masahiko
In:
ISLPED, ACM/IEEE International Symposium on Low Power Electronics and Design, 16
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219-224
;
2010
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ISBN:
- Conference paper / Storage medium
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Title:0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
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Contributors:Nakata, Yohei ( author ) / Okumura, Shunsuke ( author ) / Kawaguchi, Hiroshi ( author ) / Yoshimoto, Masahiko ( author )
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Published in:
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Publisher:
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Publication date:2010
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Size:6 Seiten, 13 Bilder, 4 Tabellen, 11 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Storage medium
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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