A new wafer surface charge monitor (CHARM) (English)
- New search for: McCarthy, A.M.
- New search for: Lukaszek, W.
- New search for: McCarthy, A.M.
- New search for: Lukaszek, W.
In:
ICMTS 1989. Proceedings of the 1989 International Conference on Microelectronic Test Structures
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153-155
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1989
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ISBN:
- Conference paper / Print
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Title:A new wafer surface charge monitor (CHARM)
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Additional title:Ein neuer Oberflaechenladungsmonitor fuer Halbleiterscheiben
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Contributors:McCarthy, A.M. ( author ) / Lukaszek, W. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Place of publication:New York
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Publication date:1989
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Size:3 Seiten
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:LADUNGSMESSUNG , PRUEFSTRUKTUR , OBERFLAECHENLADUNG , HALBLEITERSCHEIBE , MESSEN ELEKTRISCHER GROESSEN , HALBLEITERTECHNOLOGIE , EEPROM (FESTWERTSPEICHER) , FERTIGUNGSUEBERWACHUNG , IONENIMPLANTATION , UEBERWACHUNG , IONENAETZEN , EPROM (FESTWERTSPEICHER) , PRUEFUNG INTEGRIERTER SCHALTUNGEN , PROCESS STEPS
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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ICMTS 1989. Proceedings of the 1989 International Conference on Microelectronic Test Structures (Cat. No.89CH2693-0)| 1989
- 3
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Gate dimension characterization using the inversion layerFreeman, G. / Lukaszek, W. et al. | 1989
- 7
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Off-line photolithographic parameter extraction using electrical test structuresCork, C.M. et al. | 1989
- 15
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Analysis of the determination of the dimensional offset of conducting layers and MOS transistorsSwaving, S. / Klauw, K.L.M. van der / Joosten, J.J.M. et al. | 1989
- 23
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A floating gate method for MOS transistor gate capacitance and Leff measurements and its implementation in a parametric testKazerounian, R. / Singh, A. / Eltan, B. et al. | 1989
- 31
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High speed measurement of FET Vth at low IdNorimatsu, H. et al. | 1989
- 35
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Parameter extraction for a SPICE II VDMOS modelFernandez, J. / Hidalgo, S. / Berta, F. / Paredes, J. / Rebollo, J. / Millan, J. / Serra-Mestres, F. et al. | 1989
- 39
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Standardization of CMOS unit process developmentWeber, C. et al. | 1989
- 45
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The INMOS integrated parametric test and analysis systemCheung, D. / Clark, A. / Starr, R. et al. | 1989
- 51
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Test masks for micromachining siliconPuers, B. / Sansen, W. et al. | 1989
- 55
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An expert system for process diagnosis (MOS product testing)Hamilton, A. / Schofield, R. et al. | 1989
- 61
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MOSFET effective dimensions determination for VLSI process evaluationTuinhout, H.P. et al. | 1989
- 65
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Subtleties of SPICE MOSFET parameter extractionBendix, P. et al. | 1989
- 69
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Full characterization of MOS transistors in CMOS technologiesPelloie, J.L. et al. | 1989
- 73
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Enhanced MOS parameter extraction and SPICE modelling for mixed analogue and digital circuit simulationAnkele, B. / Holzl, W. / O'Leary, P. et al. | 1989
- 79
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Area-periphery partitioning of currents in self-aligned silicon bipolar transistorsFertsch, J. / Weng, J. / Miura-Mattausch, M. et al. | 1989
- 85
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A fast measurement technique for the determination of small signal parameters of the bipolar transistorVandeloo, P. et al. | 1989
- 93
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Fault simulation for fault-tolerant multi-Mbit RAMsStapper, C.H. et al. | 1989
- 97
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Evaluation technique of gate oxide reliability with electrical and optical measurementsUraoka, Y. / Tsutsu, N. / Morii, T. / Nakata, Y. / Esaki, H. et al. | 1989
- 103
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Effects of interface traps and bulk traps in SiO2 on hot-carrier-induced degradationUchida, H. / Inomata, S. / Ajioka, T. et al. | 1989
- 109
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MOSFET interface state densities of different technologiesHofmann, F. / Krautschneider, W. et al. | 1989
- 115
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Contact electromigration: a method to characterize test structures for reliability parameter estimationCaprile, C. / Specchiulli, G. et al. | 1989
- 121
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Thermal conductivity measurements of thin-film silicon dioxideSchafft, H.A. / Suehle, J.S. / Mirel, P.G.A. et al. | 1989
- 129
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An overlay vernier and process bias monitor measured by voltage contrast SEMSprogis, E.J. et al. | 1989
- 133
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The effect of contact geometry on the value of contact resistivity extracted from Kelvin structuresFindlay, K.W.J. / Alexander, W.J.C. / Walton, A.J. et al. | 1989
- 139
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Measurement of misalignment using a triangular MOS transistorLozano, M. / Cane, C. / Cabruja, E. / Gracia, I. / Lora-Tamayo, E. / Serra-Mestres, F. et al. | 1989
- 143
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Test structure for evaluation of 1/f noise in CMOS technologiesChang, Z.Y. / Sansen, W. et al. | 1989
- 147
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Test structure for measurement of conductive film thicknessHanes, M.H. / Cresswell, M.W. / Schmidt, D.N. / Fiedor, R.J. et al. | 1989
- 153
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A new wafer surface charge monitor (CHARM)McCarthy, A.M. / Lukaszek, W. et al. | 1989
- 157
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Electrical characterization of minority carrier transport parameters in n-type heavily doped siliconBellone, S. / Busatto, G. / Ransom, C.M. et al. | 1989
- 163
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Design and implementation of channel mobility measurement modulesOuwerling, G.J.L. / Staalenburg, J.C. et al. | 1989
- 169
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A simple test structure for measuring substrate resistivityOrchard-Webb, J.H. / Cloutier, R. et al. | 1989
- 175
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A new test structure for in-depth lifetime profiling of thin Si epitaxial layersSpirito, P. / Bellone, S. / Ransom, C.M. / Busatto, G. / Cocorullo, G. et al. | 1989
- 181
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CMOS process uniformity evaluation through the characterisation of parasitic transistorsWilson, D. / Walton, A.J. / Robertson, J.M. / Holwill, R.J. et al. | 1989
- 189
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Standard error in die yield projections from defect test structuresMitchell, M.A. / Sullwold, J. / Figura, C. / Forner, L. et al. | 1989
- 193
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Automating and sequencing C-V measurements for process fault diagnosis using a pattern-recognition approach (MOS test structure)Walls, J.A. / Walton, A.J. / Robertson, J.M. / Crawford, T.M. et al. | 1989
- 201
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A neural network approach for classifying test structure resultsKhera, D. / Zaghoul, M.E. / Linholm, L.W. / Wilson, C.L. et al. | 1989
- 205
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Automatic parameter extraction system with process failure diagnostics for CMOS processPieczynski, J. / Vogt, H. et al. | 1989
- 211
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Statistical worst-case MOS parameter extractionBolt, M.J.B. / Trip, A. / Verhagen, H.J. et al. | 1989
- 217
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Analysis of intra-level isolation test structure data by multiple regression facilitate rule identification for diagnostic expert systemsFreidhoff, C.B. / Cresswell, M.W. / Lowry, L.R. / Irani, K.B. et al. | 1989
- 225
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A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurementsLippe, K. / Kerkhoff, H. / Kloppers, G. / Morskieft, N. et al. | 1989
- 227
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Inverter propagation delay measurements using timing sampler circuitsBlaes, B.R. / Buehler, M.G. et al. | 1989
- 233
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An experimental measurement technique of interconnection RC delay for integrated circuits using the step voltage responseSantos, F.S.G. dos / Swart, J.W. et al. | 1989
- 239
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An opamp as a tool for testingSansen, W. / Opt Eynde, F. / Gielen, G. et al. | 1989
- 245
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Novel test structure to study location of breakdown for trench capacitorKishi, K. / Yoshida, T. / Watanabe, T. / Tanaka, T. / Shinozaki, S. et al. | 1989
- 251
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Critical charge model for transient latch-up in VLSI CMOS circuitsReczek, W. / Winnerl, J. / Pribyl, W. et al. | 1989
- 255
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Electrostatic discharge test structures for CMOS circuitsTerletzki, H. / Risch, L. et al. | 1989
- 261
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Drain and bulk symmetry factor: a statistical tool to improve device reliabilityDars, P. / d'ouville, T.T. / Merckel, G. / Mingam, H. et al. | 1989