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Synonyms were used for: Architektur
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Used synonyms:
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0.8/2.2-GHz Programmable Active Bandpass Filters in InP/Si BiCMOS Technology
Online Contents | 2015|Keywords: active-RC architecture -
3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability
Online Contents | 2015|Keywords: Computer architecture -
76-81-GHz CMOS Transmitter With a Phase-Locked-Loop-Based Multichirp Modulator for Automotive Radar
Online Contents | 2015|Keywords: frequency-doubling architecture -
85.9 Gb/in ^} Recording Areal Density on Barium Ferrite Tape
Online Contents | 2015|Keywords: iterative decoding architecture -
170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier
Online Contents | 2015|Keywords: Computer architecture -
256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
Online Contents | 2017|Keywords: Computer architecture -
A 0.5 V 55 \mu \text 64 \times 2 Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
Online Contents | 2016|Keywords: Systems architecture -
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter
Online Contents | 2015|Keywords: MASH architecture, multistage-noise-shaping architecture -
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS
Online Contents | 2015|Keywords: phase-locked loop architecture -
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques
Online Contents | 2015|Keywords: memory architecture, multichannel-per-die architecture -
A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer
Online Contents | 2017|Keywords: high-speed successive-approximation-register (SAR) architecture -
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Online Contents | 2015|Keywords: Computer architecture -
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
Online Contents | 2017|Keywords: Computer architecture -
A 1.7 ps Equivalent Bin Size and 4.2 ps RMS FPGA TDC Based on Multichain Measurements Averaging Method
Online Contents | 2015|Keywords: Computer architecture -
A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS
Online Contents | 2015|Keywords: dual-mixer architecture -
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications
Online Contents | 2015|Keywords: heterogeneous SIMD multicore architecture, pipelined multicore architecture, AR processor architecture -
A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS
Online Contents | 2015|Keywords: Computer architecture, massively parallel reconfigurable current-mode analog architecture -
A 2.89 \mu W Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications
Online Contents | 2016|Keywords: Systems architecture -
A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 \mu m CMOS
Online Contents | 2017|Keywords: Computer architecture -
A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA
Online Contents | 2016|Keywords: Computer architecture
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