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Formal reasoning on fault coverage of fault tolerant techniques: A case study
National licenceSpringer Verlag | 1994| -
Towards automatic temporal logic verification of value passing process algebra using abstract interpretation
National licenceSpringer Verlag | 1996| -
A Formal Verification Environment for Railway Signaling System Design
National licenceSpringer Verlag | 1998| -
Feature Articles - Design Validation of Embedded Dependable Systems - Integrating components for complex embedded systems will require the ability to preserve properties and verity them.
Online Contents | 2001|Contributors: Fantechi, Alessandro -
Natural Language Processing of Patents and Technical Documentation
Free accessSpringer Verlag | 2004|
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