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Emulating the GLink Chip Set With FPGA Serial Transceivers in the ATLAS Level-1 Muon Trigger
Online Contents | 2010| -
Characterizing Jitter Performance of Multi Gigabit FPGA-Embedded Serial Transceivers
Online Contents | 2010| -
Monitoring the Event-Building Features of the ATLAS RPCs ROD With an Embedded Microprocessor
Online Contents | 2010| -
DATA ACQUISITION SYSTEMS - Beyond 320 Mbyte-s With 2eSST and Bus Invert Coding on VME64x
Online Contents | 2008| -
Balancing Energy Consumption for the Establishment of Multi-interface Networks
British Library Conference Proceedings | 2015| -
DATA ACQUISITION SYSTEMS - Bus-Invert Coding for Low Noise, Low Power 2eSST VME64x Block Transfers
Online Contents | 2007| -
TRIGGER AND EVENT SELECTION - The Trigger Supervisor of the ARGO-YBJ Detector
Online Contents | 2006| -
DATA TRANSFER AND FAST NETWORKS - Do's and Don'ts With the Agilent's G-Link Chipset
Online Contents | 2006| -
DATA ACQUISITION SYSTEMS - Signal Integrity and Timing Issues of VME64x Double Edge Cycles
Online Contents | 2006|
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