-Test: Perfect Hashed Index Test for Test Response Validation (English)
- New search for: Gupta, R.
- New search for: IEEE; Computer Society
- New search for: IEEE; Circuits and Systems Society
- New search for: Gupta, R.
- New search for: IEEE; Computer Society
- New search for: IEEE; Circuits and Systems Society
In:
VLSI in computers and processors
;
588-591
;
1993
-
ISBN:
-
ISSN:
- Conference paper / Print
-
Title:-Test: Perfect Hashed Index Test for Test Response Validation
-
Contributors:
-
Conference:International conference on computer design, VLSI in computers and processors ; 1993 ; Cambridge; MA
-
Published in:VLSI in computers and processors ; 588-591
-
Publisher:
- New search for: IEEE Computer Society Press
-
Publication date:1993-01-01
-
Size:4 pages
-
Remarks:Also known as ICCD '93. IEEE Cat no 93CH3335-7
-
ISBN:
-
ISSN:
-
Type of media:Conference paper
-
Type of material:Print
-
Language:English
-
Keywords:
-
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
-
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93| 1993
- 6
-
Symbolic Analysis Methods for Masks, Circuits, and SystemsBryant, R. E. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 10
-
Wearable Computers: Merging Information Space with the WorkspaceSiewiorek, D. P. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 14
-
Design for Testability: Today and in the FutureWilliams, T. W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 16
-
A Recursive Technique for Computing Lower-Bound Performance of SchedulesLangevin, M. / Cerny, E. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 21
-
Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow GraphsHu, Y. / Ghouse, A. / Carlson, B. S. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 25
-
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling ProblemChaudhuri, S. / Walker, R. A. / Mitchell, J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 32
-
A Split Data Cache for Superscalar ProcessorsBoleyn, R. / Debardelaben, J. / Tiwari, V. / Wolfe, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 40
-
About Set and Skewed Associativity on Second-Level CachesSeznec, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 44
-
An Intelligent I-Cache Prefetch MechanismYoung, H. C. / Shekita, E. J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 54
-
Hardware Verification Using Symbolic State Transition GraphsChen, P. / Shyu, J.-M. / Chen, L.-G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 58
-
Towards a Methodology for the Formal Hierarchical Verification of RISC ProcessorsTahar, S. / Kumar, R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 63
-
AMBIANT: Automatic Generation of Behavioral Modifications for TestabilityVishakantaiah, P. / Thomas, T. / Abraham, J. A. / Abadir, M. S. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 68
-
An Analysis of Path Sensitization CriteriaSilva, J. P. M. / Sakallah, K. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 73
-
A Path Sensitization Approach to Area ReductionChen, H.-C. / Cheng, S. W. / Hsu, Y.-C. / Du, D. H. C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 77
-
Statistical Timing Optimization of Combinational Logic CircuitsJyu, H.-F. / Malik, S. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 81
-
Fidelity and Near-Optimality of Elmore-Based Routing ConstructionsBoese, K. D. / Kahng, A. B. / McCoy, B. A. / Robins, G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 86
-
Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000Diep, T. A. / Lipasti, M. H. / Shen, J. P. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 94
-
Determining Cost-Effective Multiple Issue Processor DesignsConte, T. M. / Mangione-Smith, W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 102
-
Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt MethodsWang, C.-J. / Emnett, F. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 106
-
Speculative Execution and Reducing Branch Penalty in a Parallel Issue MachineAndo, H. / Nakanishi, C. / Machida, H. / Hara, T. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 116
-
An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application SoftwareRoth, R. / Watkins, J. / Hsieh, M. / Radke, W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 126
-
Speculative Computation for Coprocessor SynthesisHoltmann, U. / Ernst, R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 132
-
Evaluation of an Object-Caching Coprocessor Design for Object-Oriented SystemsChang, J. M. / Gehringer, E. F. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 140
-
The Spring Scheduling Co-Processor: A Scheduling AcceleratorBurleson, W. / Ko, J. / Niehaus, D. / Ramamritham, K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 146
-
A Partial Scan Cost Estimation Method at the System LevelChiu, S. / Papachristou, C. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 151
-
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial ScanBhatia, S. / Jha, N. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 155
-
Bit-Splitting for Testability Enhancement in Scan-Based DesignXie, X. / Albicki, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 159
-
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic CircuitsWey, C.-L. / Shieh, M.-D. / Fisher, P. D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 166
-
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsAmon, T. / Hulgaard, H. / Burns, S. M. / Borriello, G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 174
-
An Efficient Unique State Coding Algorithm for Signal Transition GraphsPastor, E. / Cortadella, J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 178
-
A Comparison of Synchronous and Asynchronous FSMD DesignsAuletta, R. / Reese, B. / Traver, C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 184
-
SMAC: A Scene Matching ChipRanganathan, N. / Sastry, R. / Venkatesan, R. / Yoder, J. W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 188
-
Hardware Self-Tuning and Circuit Performance MonitoringKehl, T. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 193
-
Fault-Tolerant Content Addressable MemoryLo, J. C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 198
-
A 400 MHz Wave-Pipelined 8 x 8-Bit Multiplier in CMOS TechnologyGhosh, D. / Nandy, S. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 202
-
A 8.8-ns 54 x 54-Bit Multiplier Using New Redundant Binary ArchitectureMakino, H. / Nakase, Y. / Shinohara, H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 206
-
A C-Testable Carry-Free DividerSrinivas, H. R. / Vinnakota, B. / Parhi, K. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 216
-
A New High Performance Field Programmable Gate Array FamilyWhitney, T. / Schlageter, J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 220
-
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAsRoy, K. / Nag, S. / Dutta, S. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 224
-
A Reconfiguration-Based Yield Enhancement SystemNarasimhan, J. / Nakajima, K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 230
-
Efficient Verification of Symmetric Concurrent SystemsIp, C. N. / Dill, D. L. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 235
-
Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL EnvironmentSubrahmanyam, P. A. / Espinalt, J. M. / Yu, M.-L. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 242
-
Synthesis of Controllers from Interval Temporal Logic SpecificationFujita, M. / Kono, S. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 248
-
The PowerPC 601 Design MethodologyBrodnax, T. / Schiffli, M. / Watson, F. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 253
-
Design Methodology for GMICRO[TM]/500 TRON MicroprocessorNarita, S. / Arakawa, F. / Uchiyama, K. / Kawasaki, I. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 258
-
Design of the Intel Pentium[TM] ProcessorSaini, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 264
-
VLSI Design of On-Line Add/Multiply AlgorithmsSkaf, A. / Guyot, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 268
-
A Note About the Correction Cycle of High Radix Booth's MultiplicationGuo, G. / Ashtijou, M. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 272
-
Hybrid Number Representations with Bounded Carry Propagation ChainsPhatak, D. S. / Koren, I. / Choi, H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 278
-
A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-IIISakano, T. / Matsumoto, T. / Noguchi, K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 284
-
A Vector Memory System Based on Wafer-Scale Integrated Memory ArraysChiueh, T.-C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 289
-
A Novel Clock Distribution System for CMOS VLSIIshibashi, K. / Hayashi, T. / Doi, T. / Masuda, N. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 294
-
An Efficient Symbolic Design Verification SystemPark, J. / Mercer, M. R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 299
-
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition RelationCabodi, G. / Camurati, P. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 304
-
Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based VerificationJain, P. / Gopalakrishnan, G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 310
-
Reducing the Cost of Test Pattern Generation by Information ReusingLi, W. / McCrosky, C. / Abd-El-Barr, M. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 314
-
A Comparative Evaluation of Adders Based on Performance and TestabilityJayabharathi, R. / Thomas, T. / Swartzlander, E. E. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 318
-
Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design EnvironmentNaiknaware, R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 324
-
A Memory Controller with an Integrated Graphics ProcessorWatkins, J. / Roth, R. / Hsieh, M. / Radke, W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 339
-
Trail: A Track-Based Logging Disk Architecture for Zero-Overhead WritesChiueh, T.-C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 344
-
Multiple-Page Translation for TLBLiu, L. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 352
-
Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage SourcesLin, P.-S. / Zukowski, C. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 357
-
ACES: A Transient Simulation Strategy for Integrated CircuitsDevgan, A. / Rohrer, R. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 361
-
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate SimulationRiepe, M. A. / Silva, J. P. M. / Sakallah, K. A. / Brown, R. B. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 366
-
Optimal Scheduling of Finite-State MachinesYen, T.-Y. / Wolf, W. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 370
-
Global Mobility Based SchedulingPrabhu, U. / Pangrle, B. M. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 374
-
Cluster-Oriented Scheduling in Pipelined Data Path SynthesisChang, C.-T. / Rose, K. / Walker, R. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 379
-
Library-Adaptively Integrated Data Path Synthesis for DSP SystemsJou, J.-M. / Kuang, S.-R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 384
-
Economics in Design and TestDislis, C. / Ambler, A. P. / Dear, I. D. / Dick, J. H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 388
-
Design Guidelines and Testability AssessmentWilkins, B. R. / Shi, C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 394
-
String Matching on IDP: A String Matching Algorithm for Vector Processors and Its ImplementationMishina, Y. / Kojima, K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 402
-
A Systolic Array for Approximate String MatchingSastry, R. / Ranganathan, N. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 406
-
A Systolic Architecture for High Speed Pipelined MemoriesDickinson, A. G. / Nicol, C. J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 410
-
Pica: An Ultra-Light Processor for High-Throughput ApplicationsWills, D. S. / Lacy, W. S. / Cat, H. / Hopper, M. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 416
-
Logic Optimization with Multi-Output GatesWatanabe, Y. / Guerra, L. / Brayton, R. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 421
-
Low-Power Driven Technology Mapping under Timing ConstraintsLin, B. / De Man, H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 428
-
Heuristic Minimization of Synchronous RelationsSinghal, V. / Watanabe, Y. / Brayton, R. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 438
-
Derivation of a DRAM Memory Interface by Sequential DecompositionRath, K. / Bose, B. / Johnson, S. D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 442
-
Physically Realizable Gate ModelsStephan, P. R. / Brayton, R. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 446
-
Formal Semantics of VHDL for Verification of Circuit DesignsHua, G. X. / Zhang, H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 452
-
Fast Timing Analysis for Hardware-Software Co-SynthesisYe, W. / Ernst, R. / Benner, T. / Henkel, J. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 458
-
System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software DecompositionBose, B. / Tuna, M. E. / Johnson, S. D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 462
-
Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design ProjectHagen, K. T. / Meyr, H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 468
-
Strongly NP-Hard Discrete Gate Sizing ProblemsLi, W. N. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 472
-
An Exact Rectilinear Steiner Tree AlgorithmSalowe, J. S. / Warme, D. M. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 476
-
Neighbour State Transition Method for VLSI Optimization ProblemsZhou, D. / Tsui, F. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 482
-
The Splash 2 Processor and ApplicationsArnold, J. M. / Buell, D. A. / Hoang, D. T. / Pryor, D. V. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 486
-
Beyond Superscalar Using FPGAsIseli, C. / Sanchez, E. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 491
-
A Field Programmable Accelerator for Compiled-Code ApplicationsLewis, D. M. / Van Ierssel, M. H. / Wong, D. H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 498
-
High Performance Embedded System Optimization Using Algebraic and Generalized Retiming TechniquesPotkonjak, M. / Dey, S. / Iqbal, Z. / Parker, A. C. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 505
-
Some Results on the Complexity of Boolean Functions for Table Look Up ArchitecturesMurgai, R. / Brayton, R. K. / Sangiovanni-Vincentelli, A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 513
-
Efficient Symbolic Support ManipulationLin, B. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 518
-
Design for Testability of Asynchronous Sequential CircuitsSaxena, J. / Pradhan, D. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 523
-
Pseudoexhaustive BIST for Sequential CircuitsKagaris, D. / Tragoudas, S. / Bhatia, D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 528
-
Test Path Generation and Test Scheduling for Self-Testable DesignsOrailoglu, A. / Harris, I. G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 534
-
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier ReliabilityLi, P.-C. / Hajj, I. N. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 538
-
A Logic-Level Model for -Particle Hits in CMOS CircuitsCha, H. / Patel, J. H. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 543
-
Complex Gate Performance Improvement by Jog Insertion into Transistor GatesHindmarsh, R. D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 548
-
A Framework for Specifying and Designing PipelinesAagaard, M. / Leeser, M. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 552
-
System-Level Specification of Instruction SetsCook, T. A. / Franzon, P. D. / Harcourt, E. A. / Miller, T. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 558
-
Newton: Performance Improvement Through Comparative AnalysisKipp, L. D. / Kuck, D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 564
-
Pipelines Fault Simulation on Parallel Machines Using the Circuit Flow GraphTai, S.-E. / Bhattacharya, D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 568
-
MIXER: Mixed-Signal Fault SimulatorNagi, N. / Chatterjee, A. / Abraham, J. A. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 572
-
Functional Fault Models and Gate Level Coverage for Sequential ArchitecturesBuonanno, G. / Fummi, F. / Sciuto, D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 576
-
An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault SimulationFarinetti, L. / Montessoro, P. L. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 584
-
Influence of Error Correlations on the Signature Analysis AliasingLeveugle, R. / Delord, X. / Saucier, G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 588
-
-Test: Perfect Hashed Index Test for Test Response ValidationGupta, R. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 592
-
Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor SystemsSrinivasan, S. / Jha, N. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 596
-
Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation EnvironmentsVargas, F. / Nicolaidis, M. / Courtois, B. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 602
-
Fast CRC CalculationGlaise, R. J. / Jacquart, X. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 606
-
Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive FiltersChatterjee, A. / Roy, R. K. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 610
-
Subterranean: A 600 Mbit/Sec Cryptographic VLSI ChipClaesen, L. / Daemen, J. / Genoe, M. / Peeters, G. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993
- 614
-
A New Modulo 2^a + 1 MultiplierWrzyszcz, A. / Milford, D. / IEEE; Computer Society / IEEE; Circuits and Systems Society et al. | 1993