Yield Improvement by Test Error Cancellation (English)
- New search for: Wang, M.-J.
- New search for: Chang, Y.-S.
- New search for: Chen, J. E.
- New search for: Chen, Y.-E.
- New search for: Wang, M.-J.
- New search for: Chang, Y.-S.
- New search for: Chen, J. E.
- New search for: Chen, Y.-E.
In:
Asian test symposium
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258-262
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1996
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Yield Improvement by Test Error Cancellation
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Contributors:
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Conference:5th, Asian test symposium ; 1996 ; Hsinchu; Taiwan
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Published in:Asian test symposium ; 258-262PROCEEDINGS OF THE ASIAN TEST SYMPOSIUM ; 5 ; 258-262
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Publisher:
- New search for: IEEE
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Place of publication:Piscataway
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Publication date:1996-01-01
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Size:5 pages
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 4
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Redundancy Indentification Using Transitive ClosureAgrawal, V. D. / Bushnell, M. L. / Lin, Q. et al. | 1996
- 10
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Invalid State Identification for Sequential Circuit Test GenerationLiang, H.-C. / Lee, C. L. / Chen, J. E. et al. | 1996
- 16
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On Test Generation for Interconnected Finite-State Machines - the Input Sequence Propagation ProblemPomeranz, I. / Reddy, S. M. et al. | 1996
- 22
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Hierarchical Test Generation with Built-In Fault DiagnosisStroobandt, D. / Van Campenhout, J. et al. | 1996
- 29
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Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and RestrictorsVan der Linden, J. T. / Konijnenburg, M. H. / Van de Goor, A. J. et al. | 1996
- 34
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E-Groups: A New Technique for Fast Backward Propagation in System-Level Test GenerationNicolaidis, M. / Parekhji, R. A. / Boudjit, M. et al. | 1996
- 42
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Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust TestingHur, Y.-M. / Shin, J.-H. / Lee, K.-H. / Son, Y.-S. et al. | 1996
- 44
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Hybrid Pin Control Using Boundary-Scan and Its ApplicationsKe, W. et al. | 1996
- 50
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Hierarchical Testing Using the IEEE Std. 1149.5 Module Test and Maintenance Slave Interface ModelHong, J.-H. / Tsai, C.-H. / Wu, C.-W. et al. | 1996
- 56
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Testing and Diagnosis of Board Interconnects in Microprocessor-Based SystemsHsu, P.-C. / Wang, S.-J. et al. | 1996
- 62
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Syndrome Simulation and Syndrome Test for Unscanned InterconnectsSu, C. / Hwang, S.-S. / Jou, S.-J. / Ting, Y.-T. et al. | 1996
- 68
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A Test Methodology for Interconnect Structures of LUT-Based FPGAsMichinishi, H. / Yokohira, T. / Okamoto, T. / Inoue, T. et al. | 1996
- 75
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Testable Design and Testing of MCMs Based on Multifrequency ScanTseng, W.-D. / Wang, K. et al. | 1996
- 82
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A Consistent Scan Design System for Large-Scale ASICsKonno, K. / Nakamura, K. / Bitoh, T. / Saga, K. et al. | 1996
- 88
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A Design for Testability Method Using RTL PartitioningHosokawa, T. / Kawaguchi, K. / Ohta, M. / Muraoka, M. et al. | 1996
- 94
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Partially Parallel Scan Chain for Test Length Reduction by Using Retiming TechniqueHigami, Y. / Kajihara, S. / Kinoshita, K. et al. | 1996
- 100
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Combination of Automatic Test Pattern Generation and Built-In Intermediate Voltage Sensing for Detecting CMOS Bridging FaultsLee, K.-J. / Tang, J.-J. / Huang, T.-C. / Tsai, C.-L. et al. | 1996
- 107
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On Design of Fail-Safe Cellular ArraysKamiura, N. / Hata, Y. / Yamato, K. et al. | 1996
- 113
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Concurrent Error Detection and Fault Location in a Fast ATM SwitchChoi, Y.-H. / Lee, P.-G. et al. | 1996
- 119
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Formal Verification of Self-Testing Properties of Combinational CircuitsKawakubo, K. / Tanaka, K. / Hiraishi, H. et al. | 1996
- 123
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Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected GraphsLuo, Y. / Yang, S. / Hu, D. et al. | 1996
- 130
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An Approach to the Synthesis of Synchronizable Finite State Machines with Partial ScanInoue, T. / Masuzawa, T. / Youra, H. / Fujiwara, H. et al. | 1996
- 136
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Waveform Polynomial Manipulation Using BDDsZhao, Z. / Li, Z. / Min, Y. et al. | 1996
- 142
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Easily Testable Data Path Allocation Using Input/Output RegistersHuang, L.-R. / Jou, J.-Y. / Kuo, S.-Y. / Liao, W.-B. et al. | 1996
- 148
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AND/EXOR-Based Synthesis of Testable KFDD-Circuits with Small DepthHengster, H. / Drechsler, R. / Eckrich, S. / Pfeiffer, T. et al. | 1996
- 155
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Minimal Delay Test Sets for Unate Gate NetworksSparmann, U. / Mueller, H. / Reddy, S. M. et al. | 1996
- 165
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Two Modeling Techniques for CMOS Circuits to Enhance Test Generation and Fault Simulation for Bridging FaultsLee, K.-J. / Tang, J.-J. et al. | 1996
- 171
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Algorithmic Test Generation for Supply Current Testing of TTL Combinational CircuitsKuchii, T. / Hashizume, M. / Tamesada, T. et al. | 1996
- 177
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An Efficient Compact Test Generator for IDDQ TestingKondo, H. / Cheng, K.-T. et al. | 1996
- 183
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Realistic Linked Memory Cell Array FaultsVan de Goor, A. J. / Gaydadjiev, G. N. et al. | 1996
- 189
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On Current Testing of Josephson Logic Circuits Using the 4JL Gate FamilyYamada, T. / Sasaki, T. et al. | 1996
- 197
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Plenary Session: Keynote Speech - "Built-In Self-Test for Analog and Mixed-Signal Designs"Jou, J.-Y. / Cheng, K.-T. et al. | 1996
- 199
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An Efficient PRPG Strategy by Utilizing Essential FaultsHuang, L.-R. / Jou, J.-Y. / Kuo, S.-Y. et al. | 1996
- 205
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DP-BIST: A Built-In Self-Test for DSP Data Paths - A Low Overhead and High Fault Coverage TechniqueAdham, S. M. I. / Gupta, S. et al. | 1996
- 213
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An MISR Computation Algorithm for Fast Signature SimulationLin, B.-H. / Shieh, S.-H. / Wu, C.-W. et al. | 1996
- 219
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BIST Testability Enhancment of System-Level Circuits: Experience with an Industrial DesignLai, K. / Papachristou, C. A. et al. | 1996
- 226
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Low-Complexity Fault Diagnosis under the Multiple Observation Time Testing ApproachPomerantz, I. / Reddy, S. M. et al. | 1996
- 232
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Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity ComputationWei, T. / Wong, M. W. T. / Lee, Y. S. et al. | 1996
- 238
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A Practical Implementation of Dynamic Testing of an AD ConverterTing, Y. T. / Chao, L. W. / Chao, W. C. et al. | 1996
- 244
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Comparison Diagnosis in Large Multiprocessor SystemsFuhrman, C. P. / Nussbaumer, H. J. et al. | 1996
- 251
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Lessons Learned from Practical Applications of BIST/B-S TechnologyJarwala, N. / Rutkowski, P. W. / Wu, S. / Yau, C. et al. | 1996
- 257
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Fault Grading MC68332 CPU Using DBCC Loop ModeDakwala, N. et al. | 1996
- 258
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Yield Improvement by Test Error CancellationWang, M.-J. / Chang, Y.-S. / Chen, J. E. / Chen, Y.-E. et al. | 1996
- 263
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A Pragmatic, Systematic and Flexible Synthesis for Testability MethodologyCastro Alves, V. / Ribeiro Antunes, A. / Marzouki, M. et al. | 1996
- 269
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A New Model with Time Constraints for Conformance Testing of Communication ProtocolsTeratani, D. / Kakuda, Y. / Kikuno, T. et al. | 1996
- 276
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Test Generation of Analog Switched-Current CircuitsWang, C.-P. / Wey, C.-L. et al. | 1996
- 282
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Thermal Monitoring of Safety-Critical Integrated SystemsSzekely, V. / Rencz, M. / Karam, J. M. / Lubaszewski, M. et al. | 1996
- 289
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A New Scheme for the Fault Diagnosis of Multiprocessor SystemsYang, X. / Chen, T. / Cao, Z. / He, Z. et al. | 1996
- 295
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On-Line Testing in Digital Neural NetworksDemidenko, S. / Piuri, V. et al. | 1996
- iii
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Proceedings of the Fifth Asian Test Symposium (ATS'96)| 1996