Very High Performance 50nm CMOS at Low Temperature (English)
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- New search for: Wind, S. J.
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- New search for: Lee, K.-L.
- New search for: Roy, R.
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In:
International electron devices meeting
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928-930
;
1999
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ISBN:
- Conference paper / Print
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Title:Very High Performance 50nm CMOS at Low Temperature
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Contributors:Wind, S. J. ( author ) / Shi, L. ( author ) / Lee, K.-L. ( author ) / Roy, R. ( author ) / Zhang, Y. ( author ) / Sikorski, E. ( author ) / Kozlowski, P. ( author ) / D'emic, C. ( author ) / Bucchignano, J. ( author ) / Wann, H.-J. ( author )
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Conference:International electron devices meeting ; 1999 ; Washington, DC
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Published in:International electron devices meeting ; 928-930INTERNATIONAL ELECTRON DEVICES MEETING ; 928-930
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Publisher:
- New search for: IEEE
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Publication date:1999-01-01
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Size:3 pages
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Remarks:IEEE cat no 99CH36318 and 99CB36318
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ISBN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_3
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International Electron Devices Meeting 1999. Technical Digest [Front Matter and Table of Contents]| 1999
- 1.3.1
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Sorting of biontolecules via microdevicesChia-Fu Chou, / Bakajin, O. / Castelino, J.A. / Cox, E.C. / Craighead, H. / Darton, N. / Jongyoon Han, / Tegenfeldt, J.O. / Turner, S. et al. | 1999
- 1_7
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Author index| 1999
- 3
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Consumer electronics as silicon engineKramer, R. et al. | 1999
- 8
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SoC solutions and technologies for digital hypermedia platformKohyama, S. et al. | 1999
- 14
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Sorting of Biomolecules via MicrodevicesAustin, R. / IEEE et al. | 1999
- 25
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A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 GbGruening, U. / Radens, C.J. / Mandelman, J.A. / Michaelis, A. / Seitz, M. / Arnold, N. / Lea, D. / Casarotto, D. / Knorr, A. / Halle, S. et al. | 1999
- 29
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A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generationsUh, H.S. / Song, S.H. / Park, B.J. / Oh, J.H. / Chun, Y.S. / Kwak, D.H. / Hwang, Y.S. / Lee, K.H. / Jeong, H.S. / Chung, T.Y. et al. | 1999
- 33
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Extending trench DRAM technology to 0.15 /spl mu/m groundrule and beyondRupp, T. / Chaudhary, N. / Dev, K. / Fukuzaki, Y. / Gambino, J. / Ho, H. / Iba, J. / Ito, E. / Kiewra, E. / Kim, B. et al. | 1999
- 33
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Extending Trench DRAM Technology to 0.15mum Groundrule and BeyondRupp, T. / Chaudhary, N. / Dev, K. / Fukuzaki, Y. / Gambino, J. / Ho, H. / Iba, J. / Ito, E. / Klewra, E. / Kim, B. et al. | 1999
- 37
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Impact of the two traps related leakage mechanism on the tail distribution of DRAM retention characteristicsUeno, S. / Inoue, Y. / Inuishi, M. et al. | 1999
- 41
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An Embedded 0.405mum^2 Stacked DRAM Technology Integrated with a High-Performance 0.2mum CMOS Logic and 6-Level MetalizationYoshida, M. / Asaka, K. / Hoshino, Y. / Sugawara, Y. / Aoki, H. / Saito, M. / Imai, A. / Enomoto, H. / Kawakami, H. / Furukawa, R. et al. | 1999
- 41
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An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalizationYoshida, M. / Asaka, K. / Hoshino, Y. / Sugawara, Y. / Aoki, H. / Saito, M. / Imai, A. / Enomoto, H. / Kawakami, H. / Furukawa, R. et al. | 1999
- 45
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A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cellHamada, M. / Inoue, K. / Kubota, R. / Takeuchi, M. / Sakao, M. / Abiko, H. / Kawamoto, H. / Yamaguchi, H. / Kitamura, H. / Onishi, S. et al. | 1999
- 45
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A High-Performance 0.18-mum Merged DRAM/Logic Technology Featuring a 0.45-mum^2 Stacked Capacitor CellHamada, M. / Inoue, K. / Kubota, R. / Takeuchi, M. / Sakao, M. / Abiko, H. / Kawamoto, H. / Yamaguchi, H. / Kitamura, H. / Onishi, S. et al. | 1999
- 49
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Thermally robust dual-gate CMOS integration technologies for high-performance DRAM-embedded ASICsTogo, M. / Mogami, T. / Kubota, R. / Nobusawa, H. / Hamada, M. / Inoue, K. / Mikagi, K. / Yoshida, K. / Soda, E. / Kishi, S. et al. | 1999
- 55
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The ballistic nano-transistorTimp, G. / Bude, J. / Bourdelle, K.K. / Garno, J. / Ghetti, A. / Gossmann, H. / Green, M. / Forsyth, G. / Kim, Y. / Kleiman, R. et al. | 1999
- 59
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A new SOI MOSFET structure with junction type body contactIn-Young Chung, / Dong Soo Woo, / Young June Park, / Hong Shick Min, et al. | 1999
- 63
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A novel sidewall strained-Si channel nMOSFETLiu, K.C. / Wang, X. / Quinones, E. / Chen, X. / Chen, X.D. / Kencke, D. / Anantharam, B. / Chang, R.D. / Ray, S.K. / Oswal, S.K. et al. | 1999
- 67
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Sub 50-nm FinFET: PMOSXuejue Huang, / Wen-Chin Lee, / Charles Kuo, / Hisamoto, D. / Leland Chang, / Kedzierski, J. / Anderson, E. / Takeuchi, H. / Yang-Kyu Choi, / Asano, K. et al. | 1999
- 71
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Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxyJong-Ho Lee, / Taraschi, G. / Andy Wei, / Langdo, T.A. / Fitzgerald, E.A. / Antoniadis, D.A. et al. | 1999
- 75
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The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate lengthHergenrother, J.M. / Monroe, D. / Klemens, F.P. / Weber, G.R. / Mansfield, W.M. / Baker, M.R. / Baumann, F.H. / Bolan, K.J. / Bower, J.E. / Ciampa, N.A. et al. | 1999
- 81
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Device Reliability in Analog CMOS Applications (Invited)Thewes, R. / Brederlow, R. / Schlunder, C. / Wieczorek, P. / Hesener, A. / Ankele, B. / Klein, P. / Kessel, S. / Weber, W. / IEEE et al. | 1999
- 81
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Device reliability in analog CMOS applicationsThewes, R. / Brederlow, R. / Schlunder, C. / Wieczorek, P. / Hesener, A. / Ankele, B. / Klein, P. / Kessel, S. / Weber, W. et al. | 1999
- 85
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Mechanism for hot-carrier-induced interface trap generation in MOS transistorsHess, K. / Jinju Lee, / Lyding, J.W. / Rosenbaum, E. / Kizilyalli, I. / Chetlur, S. et al. | 1999
- 89
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Channel hot-electron and hot-hole improvement in Al and Cu multilevel metal CMOS using deuterated anneals and passivating filmsClark, W.F. / Cottrell, P.E. / Ference, T.G. / Lo, S.H. / Massey, J.G. / Mittl, S.W. / Rankin, J.H. et al. | 1999
- 93
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Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devicesMelik-Martirosian, A. / Ma, T.P. et al. | 1999
- 97
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Plasma process-induced damage in SOI devicesPoiroux, T. / Pelloie, J.L. / Turban, G. / Reimbold, G. et al. | 1999
- 101
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Investigation of plasma-induced charging damage for nMOSFETs with conventional or damascene Al interconnectsShiba, K. / Hayashi, Y. et al. | 1999
- 107
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Technology for Active Matrix Light Emitting Polymer Displays (Invited)Shimoda, T. / Kimura, M. / Seki, S. / Kobayashi, H. / Kanbe, S. / Miyashita, S. / Friend, R. / Burroughs, J. / Towns, C. / Millard, I. et al. | 1999
- 107
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Technology for active matrix light emitting polymer displaysShimoda, T. / Kimura, M. / Seki, S. / Kobayashi, H. / Kanbe, S. / Miyashita, S. / Friend, R.H. / Burroughes, J.H. / Towns, C.R. / Millard, I.S. et al. | 1999
- 111
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High-mobility, low voltage organic thin film transistorsGundlach, D.J. / Klauk, H. / Sheraw, C.D. / Chung-Chen Kuo, / Jiunn-Ru Huang, / Jackson, T.N. et al. | 1999
- 115
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Novel fabrication methods and characteristics of organic complementary circuitsCrone, B. / Dodabalapur, A. / Rogers, J. / Martin, S. / Filas, R. / Yen-Yi Lin, / Bao, Z. / Sarpeshkar, R. / Wenjie Li, / Katz, H. et al. | 1999
- 119
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High temperature polycrystalline silicon thin film transistor on steel substratesMing Wu, / Pangal, K. / Sturm, J.C. / Wagner, S. et al. | 1999
- 123
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Optical devices fabricated from porous thin films embedded with liquid crystalsSit, J.C. / Broer, D.J. / Brett, M.J. et al. | 1999
- 127
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Two-dimensional nozzle arrangement in a monolithic inkjet printhead for high-resolution and high-speed printingJae-Duk Lee, / Choon-Sup Lee, / Ki-Chul Chun, / Chul-Hi Han, et al. | 1999
- 133
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Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric applicationLaegu Kang, / Wen-Jie Qi, / Renee Nieh, / Yongjoo Jeon, / Katsunori Onishi, / Lee, J.C. et al. | 1999
- 137
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High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technologyXin Guo, / Xiewen Wang, / Zhijiong Luo, / Ma, T.P. / Tamagawa, T. et al. | 1999
- 137
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High Quality Ultra-thin (1.5 nm) TiO~2/Si~3N~4 Gate Dielectric for Deep Sub-micron CMOS TechnologyGuo, X. / Wang, X. / Luo, Z. / Ma, T. P. / Tamagawa, T. / IEEE et al. | 1999
- 141
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High Quality Ta~2O~5 Gate Dielectrics with T~o~x~,~e~q<10AngstromLuan, H. F. / Lee, S. J. / Lee, C. H. / Song, S. C. / Mao, Y. L. / Senaki, Y. / Roberts, D. / Kwong, D. L. / IEEE et al. | 1999
- 141
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High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/Luan, H.F. / Lee, S.J. / Lee, C.H. / Song, S.C. / Mao, Y.L. / Senzaki, Y. / Roberts, D. / Kwong, D.L. et al. | 1999
- 145
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MOSCAP and MOSFET Characteristics Using ZrO~2 Gate Dielectric Deposited Directly on SiQi, W.-J. / Nieh, R. / Lee, B. H. / Kang, L. / Jeon, Y. / Onishi, K. / Ngai, T. / Banerjee, S. / Lee, J. / IEEE et al. | 1999
- 145
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MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on SiWen-Jie Qi, / Renee Nieh, / Laegu Kang, / Yongjoo Jeon, / Onishi, K. / Banerjee, S. / Lee, J.C. et al. | 1999
- 149
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Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement processYanjun Ma, / Yoshi Ono, / Stecker, L. / Evans, D.R. / Hsu, S.T. et al. | 1999
- 155
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Accurate thermal noise model for deep-submicron CMOSScholten, A.J. / Tromp, H.J. / Tiemeijer, L.F. / Van Langevelde, R. / Havens, R.J. / De Vreede, P.W.H. / Roes, R.F.M. / Woerlee, P.H. / Montree, A.H. / Klaassen, D.B.M. et al. | 1999
- 159
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Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuitsBrederlow, R. / Weber, W. / Schmitt-Landsiedel, D. / Thewes, R. et al. | 1999
- 163
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A large signal non-quasi-static MOS model for RF circuit simulationScholten, A.J. / Tiemeijer, L.F. / De Vreede, P.W.H. / Klaassen, D.B.M. et al. | 1999
- 167
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A comprehensive MOSFET mismatch modelDrennan, P.G. / McAndrew, C.C. et al. | 1999
- 171
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Modeling of Pocket Implanted MOSFETs for Anomalous Analog BehaviorsCao, K. M. / Liu, W. / Jin, X. / Vasanth, K. / Green, K. / Krick, J. / Vrotsos, T. / Hu, C. / IEEE et al. | 1999
- 171
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Modeling of pocket implanted MOSFETs for anomalous analog behaviorKanyu Mark Cao, / Weidong Liu, / Xiaodong Jin, / Green, K. / Krick, J. / Vrotsos, T. / Chenming Hu, et al. | 1999
- 175
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Self-heating characterization for SOI MOSFET based on AC output conductanceWei Jin, / Fung, S.K.H. / Weidong Liu, / Chan, P.C.H. / Chenming Hu, et al. | 1999
- 179
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A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulationChung, S.S. / Yih, C.-M. / Wu, S.S. / Chen, H.H. / Gary Hong, et al. | 1999
- 185
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Current and Future Development of High Power MOS Devices (Invited)Ohashi, H. / IEEE et al. | 1999
- 185
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Current and future development of high power MOS devicesOhashi, H. et al. | 1999
- 189
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High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS processJun-Lin Tsai, / Jei-Feng Huang, / Shih-Hui Chen, / Jeng Gong, / Ruey-Hsin Liou, / Shun-Liang Hsu, et al. | 1999
- 189
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High Voltage NPN-Bipolar Transistor Using P^+-Buried Layer in BiCMOS ProcessTsai, J.-L. / Huang, J.-F. / Chen, S.-H. / Gong, J. / Liou, R.-H. / Hsu, S.-L. / IEEE et al. | 1999
- 193
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Snapback and safe operating area of LDMOS transistorsHower, P.L. / Merchant, S. et al. | 1999
- 197
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20 V and 8 V lateral trench gate power MOSFETs with record-low on-resistanceKawaguchi, Y. / Sano, T. / Nakagawa, A. et al. | 1999
- 201
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RF LDMOS with extreme low parasitic feedback capacitance and high hot-carrier immunityShuming Xu, / Pangdow Foo, / Jianqing Wen, / Yong Liu, / Fujiang Lin, / Changhong Ren, et al. | 1999
- 205
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High performance scaled down Si LDMOSFET with thin gate bird's beak technology for RF power amplifiersHoshino, Y. / Morikawa, M. / Kamohara, S. / Kawakami, M. / Fujioka, T. / Matsunaga, Y. / Kusakari, Y. / Ikeda, S. / Yoshida, I. / Shimizu, S. et al. | 1999
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High Temperature (450&unknown;C) Reliable NMISEETs on P-Type 6H-SiCWang, X. W. / Zhu, W. J. / Guo, X. / Ma, T. P. / Tucker, J. / Rao, M. / IEEE et al. | 1999
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High temperature (450/spl deg/C) reliable NMISFET's on p-type 6H-SiCWang, X.W. / Zhu, W.J. / Guo, X. / Ma, T.P. / Tucker, J.B. / Rao, M.V. et al. | 1999
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Magnetoelectronic devicesDe Boeck, J. / Borghs, G. et al. | 1999
- 215
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Magnetoelectronic Devices (Invited)De Boeck, J. / Borghs, G. / IEEE et al. | 1999
- 219
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Design and demonstration of new operation mode multi-emitter resonant tunneling hot electron transistors for one-transistor-SRAM-cell and peripheral logic circuitryTakatsu, M. / Adachihara, T. / Mori, T. / Awano, Y. / Yokoyama, N. et al. | 1999
- 223
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Resonant Fowler-Nordheim tunneling through layered tunnel barriers and its possible applicationsKorotkov, A. / Likharev, K. et al. | 1999
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Prospects for molecular-scale devicesReed, M.A. / Bennett, D.W. / Chen, J. / Grubisha, D.S. / Jones, L. / Rawlett, A.M. / Tour, J.M. / Zhou, C. et al. | 1999
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Molecular-scale rectifying diodes based on Y-junction carbon nanotubesVedeneev, A.S. / Li, J. / Papadopoulos, C. / Rakitin, A. / Bennett, A.J. / Chik, H.W. / Xu, J.M. et al. | 1999
- 234
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Memory operation of AlGaAs/GaAs heterostructure FETs with InAs quantum dots in an AlGaAs barrier layerMizutani, T. / Inayoshi, T. / Eguchi, Y. / Kishimoto, S. / Maezawa, K. et al. | 1999
- 241
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MOSFETs with 9 to 13 A thick gate oxidesKrishnan, M.S. / Tsu-Jae King, / Bokor, J. / Chenming Hu, et al. | 1999
- 241
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MOSFETs with 9 to 13Angstrom Thick Gate OxidesKrishnan, M. / Chang, L. / King, T.-J. / Bokor, J. / Hu, C. / IEEE et al. | 1999
- 245
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Integration of Ultrathin (1.6-2.0nm) RPECVD Oxynitride Gate Dielectrics into Dual Poly-Si Gate Submicron CMOSFETsYang, H. / Lucovsky, G. / IEEE et al. | 1999
- 245
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Integration of ultrathin (1.6/spl sim/2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETsYang, H. / Lucovsky, G. et al. | 1999
- 249
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Low-temperature growth of high-integrity silicon oxide films by oxygen radical generated in high-density krypton plasmaHirayama, M. / Sekine, K. / Saito, Y. / Ohmi, T. et al. | 1999
- 253
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A novel W/TiNx metal gate CMOS technology using nitrogen-concentration-controlled TiNx filmWakabayashi, H. / Saito, Y. / Takeuchi, K. / Mogami, T. / Kunio, T. et al. | 1999
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Reduction of threshold voltage deviation in Damascene metal gate MOSFETsYagishita, A. / Saito, T. / Nakajima, K. / Inumiya, S. / Matsuo, K. / Akasaka, Y. / Ozawa, Y. / Yano, H. / Matsui, Y. / Suguro, K. et al. | 1999
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Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrierMatsuki, T. / Kishimoto, K. / Fujii, K. / Itoh, N. / Yoshida, K. / Ohto, K. / Yamasaki, S. / Shinmura, T. / Kasai, N. et al. | 1999
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Cu/poly-Si Damascence Gate Structured MOSFET with Ta and TaN Stacked BarrierMatsuki, T. / Kishimoto, K. / Fujii, K. / Ihto, N. / Yoshida, K. / Ohto, K. / Yamasaki, S. / Shinmura, T. / Kasai, N. / IEEE et al. | 1999
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A High Density High Performance 180nm Generation Etox™ Flash Memory TechnologyFazio, A. / IEEE et al. | 1999
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A high density high performance 180 nm generation Etox/sup TM/ flash memory technologyFazio, A. et al. | 1999
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A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memoriesSatoh, S. / Nakamura, T. / Takeuchi, K. / Iizuka, H. / Shirota, R. et al. | 1999
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The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and flash memory cellsEsseni, D. / Selmi, L. / Ghetti, A. / Sangiorgi, E. et al. | 1999
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Highly manufacturable 1T1C 4 Mb FRAM with novel sensing schemeJung, D.J. / Jeon, B.G. / Kim, H.H. / Song, Y.J. / Koo, B.J. / Lee, S.Y. / Park, S.O. / Park, Y.W. / Kinam Kim, et al. | 1999
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A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memoriesNemati, F. / Plummer, J.D. et al. | 1999
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Surface free technology by laser annealing (SUFTLA)Shimoda, T. / Inoue, S. et al. | 1999
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Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallizationJagar, S. / Chan, M. / Poon, M.C. / Ming Qin, / Ko, P.K. / Yangyuan Wang, et al. | 1999
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Reproducible high field effect mobility polysilicon thin film transistors involving pulsed Nd:YVO/sub 4/ laser crystallizationHelen, Y. / Dassow, R. / Mourgues, K. / Bonnaud, O. / Mohammed-Brahim, T. / Raoult, F. / Koehler, J.R. / Werner, J.H. / Lemoine, D. et al. | 1999
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Reproducible High Field Effect Mobility Polysilicon Thin Film Transistors Involving Pulsed Nd:YVO~4 Laser CrystallizationHelen, Y. / Dassow, R. / Mourgues, K. / Bonnaud, O. / Mohammed-Brahim, T. / Raoult, F. / Koehler, J. / Werner, J. / Lemoine, D. / IEEE et al. | 1999
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Limit of the mobility enhancement of the excimer-laser-crystallized low-temperature poly-Si TFTsHara, A. / Sasaki, N. et al. | 1999
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Effects of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTsLin, C.W. / Yang, M.Z. / Yeh, C.C. / Cheng, L.J. / Huang, T.Y. / Cheng, H.C. / Chao, T.S. / Chang, C.Y. et al. | 1999
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Hydrogenated amorphous-silicon thin-film transistor structure with buried field plateNahm, J.-Y. / Lan, J.-H. / Kanicki, J. et al. | 1999
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Hydrogenated Amorphous-Silicon Thin-Film Transistor Structure with the Buried Field PlateNahm, J.-Y. / Lan, J.-H. / Kanicki, J. / IEEE et al. | 1999
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Soft error considerations for deep-submicron CMOS circuit applicationsCohen, N. / Sriram, T.S. / Leland, N. / Moyer, D. / Butler, S. / Flatley, R. et al. | 1999
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The metal gate MOS reliability with improved sputtering process for gate electrodeYamada, T. / Moriwaki, M. / Harada, Y. / Fujii, S. / Eriguchi, K. et al. | 1999
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The Metal Gate MOS Reliability with the Improved Sputtering Process for Gate ElectrodeYamada, T. / Moriwaki, M. / Harada, Y. / Fujii, S. / Eriguchi, K. / IEEE et al. | 1999
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Role of Bas Layer in CVD Si~3N~4 Stack Gate Dielectrics on the Process Controllability and Reliability in Direct Tunneling RegimeEriguchi, K. / Harada, Y. / Niwa, M. / IEEE et al. | 1999
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Role of base layer in CVD Si/sub 3/N/sub 4/ stack gate dielectrics on the process controllability and reliability in direct tunneling regimeEriguchi, K. / Harada, Y. / Niwa, M. et al. | 1999
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Analysis of High Voltage TDDB Measurements on Ta~2O~5/SiO~2 StackDegraeve, R. / Kaczer, B. / Houssa, M. / Groeseneken, G. / Heyns, M. / Jeon, J. S. / Halliyal, A. / IEEE et al. | 1999
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Analysis of high voltage TDDB measurements on Ta/sub 2/O/sub 5//SiO/sub 2/ stackDegraeve, R. / Kaczer, B. / Houssa, M. / Groeseneken, G. / Heyns, M. / Jeon, J.S. / Halliyal, A. et al. | 1999
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Fundamental Diffusion Issues for Deep-Submicron Device Processing (Invited)Cowern, N. / Jaraiz, M. / Cristiano, F. / Claverie, A. / Mannino, G. / IEEE et al. | 1999
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Fundamental diffusion issues for deep-submicron device processingJaraiz, M. / Cristiano, F. / Claverie, A. / Mannino, G. et al. | 1999
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Dopant redistribution in SOI during RTA: a study on doping in scaled-down Si layersHeemyong Park, / Jones, E.C. / Ronsheim, P. / Cabral, C. / D'Emic, C. / Cohen, G.M. / Young, R. / Rausch, W. et al. | 1999
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Dopant Redistribution on SOI during RTA: A Study on Doping in Scaled-down Si LayersPark, H. / Jones, E. C. / Ronsheim, P. / Cabral, C. / D'Emic, C. / Cohen, G. / Young, R. / Rausch, W. / IEEE et al. | 1999
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Anomalous diffusion of dopant in Si substrate during oxynitride processYaegashi, T. / Aoki, N. / Takeuchi, Y. / Hazama, H. / Aritome, S. / Shirota, R. et al. | 1999
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Dopant Diffusion in C-Doped Si and SiGe; Physical Model and Experimental VerficationRucker, H. / Heinemann, B. / Bolze, D. / Knoll, D. / Kruger, D. / Kurps, R. / Osten, H. / Schley, P. / Tillack, B. / Zaumseil, P. et al. | 1999
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Dopant diffusion in C-doped Si and SiGe: physical model and experimental verificationRucker, H. / Heinemann, B. / Bolze, D. / Knoll, D. / Kruger, D. / Kurps, R. / Osten, H.J. / Schley, P. / Tillack, B. / Zaumseil, P. et al. | 1999
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Two-dimensional dopant characterization using SIMS, SCS and TSUPREM4Ukraintsev, V.A. / Walsh, S.T. / Ashburn, S.P. / Machala, C.F. / Edwards, H. / Gray, J.T. / Joshi, S. / Woodall, D. / Chang, M.-C. et al. | 1999
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Predictive BSIM3v3 Modeling for the 0.15-0.18mum CMOS Technology Node: A Process DOE Based ApproachVasanth, K. / Krick, J. / Unnikrishnan, S. / Nandakumar, M. / Jacobs, J. / Ehnis, P. / Green, K. / Machala, C. / Vrotsos, T. / IEEE et al. | 1999
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Predictive BSIM3v3 modeling for the 0.15-0.18 /spl mu/m CMOS technology node: a process DOE based approachVasanth, K. / Krick, J. / Unnikrishnan, S. / Nandakumar, M. / Jacobs, J. / Ehnis, P. / Green, K. / Machala, C. / Vrotsos, T. et al. | 1999
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Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopyDombrowski, K.F. / Fischer, A. / Dietrich, B. / De Wolf, I. / Bender, H. / Pochet, S. / Simons, V. / Rooyackers, R. / Badenes, G. / Stuer, C. et al. | 1999
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Single Electron and Few Electron Memory Cells (Invited)Ahmed, H. / IEEE et al. | 1999
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Single electron and few electron memory cellsAhmed, H. et al. | 1999
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Si complementary single-electron inverterOno, Y. / Takahashi, Y. / Yamazaki, K. / Nagase, M. / Namatsu, H. / Kurihara, K. / Murase, K. et al. | 1999
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A directional current switch using silicon single electron transistors controlled by charge injection into silicon nano-crystal floating dotsTakahashi, N. / Ishikuro, H. / Hiramoto, T. et al. | 1999
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Write, erase and storage times in nanocrystal memories and the role of interface statesWahl, J.A. / Silva, H. / Gokirmak, A. / Kumar, A. / Welser, J.J. / Tiwari, S. et al. | 1999
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Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETsMajima, H. / Ishikuro, H. / Hiramoto, T. et al. | 1999
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Coulomb oscillations in 100 nm and 50 nm CMOS devicesSpecht, M. / Sanquer, M. / Caillat, C. / Guegan, G. / Deleonibus, S. et al. | 1999
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Wide Bandgap Semiconductor Microwave Technologies: From Promise to Practice (Invited)Zolper, J. / IEEE et al. | 1999
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Wide bandgap semiconductor microwave technologies: from promise to practiceZolper, J.C. et al. | 1999
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200 W GaAs-based MODFET power amplifier for W-CDMA base stationsIshida, H. / Yokoyama, T. / Furukawa, H. / Tanaka, T. / Maeda, M. / Morimoto, S. / Ota, Y. / Ueda, D. / Hamaguchi, C. et al. | 1999
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Microwave performance of AlGaN/GaN high electron mobility transistors on Si(111) substratesChumbes, E.M. / Smart, J.A. / Hogue, D. / Komiak, J. / Shealy, J.R. et al. | 1999
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Recessed gate AlGaN/GaN MODFET on sapphire grown by MOCVDJimbo, T. / Umeno, M. et al. | 1999
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A low-distortion and high-efficiency E-mode GaAs power FET based on a new method to improve device linearity focused on g/sub m/ valueNakasha, Y. / Nagahara, M. / Tateno, Y. / Takahashi, H. / Igarashi, T. / Joshin, K. / Fukaya, J. / Takikawa, M. et al. | 1999
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A Low-Distortion and High-Efficiency E-mode GaAs Power FET Based on a New Method to Improve Device Linearity Focused on g~m ValueNakasha, Y. / Nagahara, M. / Tateno, Y. / Takahashi, H. / Igarashi, T. / Joshin, K. / Fukaya, J. / Takikawa, M. / IEEE et al. | 1999
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A 25 GHz InGaAs/InAlAs-InP HBT power MMIC with 48% power added efficiencyKobayashi, K.W. / Li Yang, / Gutierrez-Aitken, A. / Kaneshiro, E. / Yamada, F.M. / Yen, H.C. / Block, T.R. / Oki, A.K. / Streit, D.C. et al. | 1999
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100 nm gate length high performance/low power CMOS transistor structureGhani, T. / Ahmed, S. / Aminzadeh, P. / Bielefeld, J. / Charvat, P. / Chu, C. / Harper, M. / Jacob, P. / Jan, C. / Kavalieros, J. et al. | 1999
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A 1.2V, Sub-0.09mum Gate Length CMOS TechnologyMehrotra, M. / Hu, J. C. / Jain, A. / Shiau, W. / Hattangady, S. / Reddy, V. / Aur, S. / Rodder, M. / IEEE et al. | 1999
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A 1.2V, sub-0.09 /spl mu/m gate length CMOS technologyMehrotra, M. / Hu, J.C. / Jain, A. / Shiau, W. / Reddy, V. / Aur, S. / Rodder, M. et al. | 1999
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Device Issues in the Integration of Analog/RF in Deep Submicron Digital CMOS (Invited)Buss, D. / IEEE et al. | 1999
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Device issues in the integration of analog/RF functions in deep submicron digital CMOSBuss, D. et al. | 1999
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High performance transistors with state-of-the-art CMOS technologiesKim, W.S. / Ha, J.M. / Lee, G.G. / Ku, J.-H. / Kim, H.S. / Kim, C.S. / Choi, C.J. / Choe, T.H. / Yoo, J.Y. / Song, W.S. et al. | 1999
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Sub-60 nm physical gate length SOI CMOSYang, I.Y. / Chen, K. / Smeys, P. / Sleight, J. / Lin, L. / Leong, M. / Nowak, E. / Fung, S. / Maciejewski, E. / Varekamp, P. et al. | 1999
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Gate Oxides in 50nm Devices: Thickness Uniformity Improves Projected Reliability (Invited)Weir, B. / Silverman, P. / Alam, M. / Baumann, F. / Monroe, D. / Ghetti, A. / Bude, J. / Timp, G. / Hamad, A. / Oberdick, T. et al. | 1999
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Gate oxides in 50 nm devices: thickness uniformity improves projected reliabilityWeir, B.E. / Silverman, P.J. / Alam, M.A. / Baumann, F. / Monroe, D. / Ghetti, A. / Bude, J.D. / Timp, G.L. / Hamad, A. / Oberdick, T.M. et al. | 1999
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Nonlinear characteristics of Weibull breakdown distributions and its impact on reliability projection for ultra-thin oxidesWu, E.Y. / Nowak, E. / Han, L.K. / Dufresne, D. / Abadeer, W.W. et al. | 1999
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A consistent model for time dependent dielectric breakdown in ultrathin silicon dioxidesOkada, K. / Yoneda, K. et al. | 1999
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Explanation of soft and hard breakdown and its consequences for area scalingAlam, M.A. / Weir, B. / Bude, J. / Silverman, P. / Monroe, D. et al. | 1999
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Analysis of tunneling currents and reliability of NMOSFETs with sub-2 nm gate oxidesYang, N. / Henson, W.K. / Wortman, J.J. et al. | 1999
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Minority Carrier Tunneling and Stress-Induced Leakage Current for p^+ gate MOS Capacitors with Poly-Si and Poly-Si~0~.~7 Ge~0~.~3 Gate MaterialHoutsma, V. / Hoellman, J. / Salm, C. / deHaan, I. / Schmitz, J. / Widdershoven, F. / Woerlee, P. / IEEE et al. | 1999
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Minority carrier tunneling and stress-induced leakage current for p/sup +/ gate MOS capacitors with poly-Si and poly-Si/sub 0.7/Ge/sub 0.3/ gate materialHoutsma, V.E. / Holleman, J. / Salm, C. / Schmitz, J. / Widdershoven, F.P. / Woerlee, P.H. et al. | 1999
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Experimental examination of physical model for direct tunneling current in unstressed/stressed ultrathin gate oxidesTakagi, S. / Takayanagi, M. / Toriumi, A. et al. | 1999
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Photo-carrier generation as the origin of Fowler-Nordheim-induced substrate hole current in thin oxidesRasras, M. / de Wolf, D. / Groeseneken, G. / Kaczer, B. / Degraeve, R. / Maes, H.E. et al. | 1999
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Toward scientific manufacturingTsujide, T. et al. | 1999
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Toward Scientific Manufacturing (Invited)Tsujide, T. / IEEE et al. | 1999
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Analysis of SRAM bit failure at high frequency operationYoshida, Y. / Funayama, K. / Nishida, A. / Sekiguchi, T. / Nakamura, K. / Tomimatsu, S. / Umemura, K. / Yamanaka, T. / Komori, K. / Mitsui, Y. et al. | 1999
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Intra-field gate CD variability and its impact on circuit performanceOrshansky, M. / Milor, L. / Ly Nguyen, / Hill, G. / Yeng Peng, / Chenming Hu, et al. | 1999
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An in-line contact and via hole inspection method using electron beam compensation currentYamada, K. / Nakamura, T. / Tsujide, T. et al. | 1999
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Tools for non-invasive optical characterization of CMOS circuitsZappa, F. / Cova, S. / Vendrame, L. et al. | 1999
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Tools for Non-Invasive Optical Characterization for CMOS CircuitsStellari, F. / Zappa, F. / Cova, S. / Vendrame, L. / IEEE et al. | 1999
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A manufacturable multiple gate oxynitride thickness technology for system on a chipLee, C.H. / Luan, H.F. / Song, S.C. / Lee, S.J. / Evans, B. / Kwong, D.L. et al. | 1999
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Silicide induced pattern density and orientation dependent transconductance in MOS transistorsSteegen, A. / Stucchi, M. / Lauwers, A. / Maex, K. et al. | 1999
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Improved PMOSFET Short-Channel Performance Using Ultra-Shallow Si~0~.~8 Ge~0~.~2 Source/Drain ExtensionsTakeuchi, H. / Lee, W. C. / Ranade, P. / King, T. J. / IEEE et al. | 1999
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Improved PMOSFET short-channel performance using ultra-shallow Si/sub 0.8/Ge/sub 0.2/ source/drain extensionsTakeuchi, H. / Wen-Chin Lee, / Ranade, P. / Tsu-Jae King, et al. | 1999
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A Novel Atomic Layer Doping Technology for Ultra-Shallow Junction in Sub-0.1 mum MOSFETsSong, Y. H. / Kim, K. Y. / Bae, J. C. / Kato, K. / Arakawa, E. / Kim, K. S. / Park, K. T. / Kurino, H. / Koyanagi, M. / IEEE et al. | 1999
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A novel atomic layer doping technology for ultra-shallow junction in sub-0.1 /spl mu/m MOSFETsSong, Y.H. / Kim, K.Y. / Bae, J.C. / Kato, K. / Arakawa, E. / Kim, K.S. / Park, K.T. / Kurino, H. / Koyanagi, M. et al. | 1999
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70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)Bin Yu, / Yun Wang, / Haihong Wang, / Qi Xiang, / Riccobene, C. / Talwar, S. / Ming-Ren Lin, et al. | 1999
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Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) processSkotnicki, T. / Gwoziecki, R. / Lenoble, D. / Ribot, P. / Paoli, M. / Martins, J. / Tormen, B. / Grouillet, A. / Pantel, R. / Galvier, J. et al. | 1999
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A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migrationSato, T. / Aoki, N. / Mizushima, I. / Tsunashima, Y. et al. | 1999
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Issues in Modeling Small Devices (Invited)Laux, S. / Fischetti, M. / IEEE et al. | 1999
- 523
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Issues in modeling small devicesLaux, S.E. / Fischetti, M.V. et al. | 1999
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Explaining the dependences of electron and hole mobilities in Si MOSFET's inversion layerPirovano, A. / Lacaita, A.L. / Oberhuber, R. et al. | 1999
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Compact and accurate quantum correction for MOS device simulatorUsuki, T. / Tanaka, T. / Ohkubo, S. / Momiyama, Y. / Futatsugi, T. / Sugii, T. et al. | 1999
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Quantum mechanical enhancement of the random dopant induced threshold voltage fluctuations and lowering in sub 0.1 micron MOSFETsAsenov, A. / Slavcheva, G. / Brown, A.R. / Davies, J.H. / Saini, S. et al. | 1999
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Statistical pn junction leakage model with trap level fluctuation for Tref (refresh time)-oriented DRAM designKamohara, S. / Kubota, K. / Moniwa, M. / Ohyu, K. / Ogishima, A. et al. | 1999
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Physics-based analysis of RF performance of small geometry MOSFETs: methodology and application to the evaluation of the effects of scalingFiegna, C. et al. | 1999
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Performance limits of silicon MOSFET'sAssad, F. / Zhibin Ren, / Datta, S. / Lundstrom, M. / Bendix, P. et al. | 1999
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12 ps implanted base silicon bipolar technologyBock, J. / Knapp, H. / Aufinger, K. / Wurzer, M. / Boguth, S. / Schreiter, R. / Meister, T.F. / Rest, M. / Ohnemus, M. / Treitinger, L. et al. | 1999
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A 0.2-/spl mu/m self-aligned SiGe HBT featuring 107-GHz f/sub max/ and 6.7-ps ECLKondo, M. / Ohue, E. / Oda, K. / Hayami, R. / Tanabe, M. / Shimamoto, H. / Harada, T. et al. | 1999
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A 0.2mum Self-Aligned SiGe HBT Featuring 107-GHz f~m~a~x and 6.7-ps ECLWashio, K. / Kondo, M. / Ohue, E. / Oda, K. / Hayami, R. / Tanabe, M. / Shimamoto, H. / Harada, T. / IEEE et al. | 1999
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Modular integration of high-performance SiGe:C HBTs in a deep submicron, epi-free CMOS processEhwald, K.E. / Knolll, D. / Heinemann, B. / Chang, K. / Mauntel, R. / Lim, I.S. / Steele, J. / Schley, P. / Tillack, B. / Wolff, A. et al. | 1999
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Very low cost graded SiGe base bipolar transistors for a high performance modular BiCMOS processKing, C.A. / Frei, M.R. / Mastrapasqua, M. / Ng, K.K. / Kim, Y.O. / Johnson, R.W. / Moinian, S. / Martin, S. / Cong, H.-I. / Klemens, F.P. et al. | 1999
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A 0.18mum 90 GHz f~r SiGe HBT BiCMOS, ASIC-Compatible, Copper Interconnect Technology for RF and Microwave ApplicationsFreeman, G. / Ahlgren, D. / Greenberg, D. / Groves, R. / Huang, F. / Hugo, G. / Jagannathan, B. / Jeng, S. J. / Johnson, J. / Schonenberg, K. et al. | 1999
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A 0.18 /spl mu/m 90 GHz f/sub T/ SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applicationsFreeman, G. / Ahlgren, D. / Greenberg, D.R. / Groves, R. / Huang, F. / Hugo, G. / Jagannathan, B. / Jeng, S.J. / Johnson, J. / Schonenberg, K. et al. | 1999
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SiGe profile design tradeoffs for RF circuit applicationsGuofu Niu, / Shiming Zhang, / Cressler, J.D. / Joseph, A.J. / Fairbanks, J.S. / Larson, L.E. / Webster, C.S. / Ansley, W.E. / Harame, D.L. et al. | 1999
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High performance 0.15 /spl mu/m self-aligned SiGe p-MOS-MODFET's with SiN gate dielectricLu, W. / Hammond, R. / Koester, S.J. / Wang, X.W. / Chu, J.O. / Ma, T.P. / Adesida, I. et al. | 1999
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High Performance 0.15mum Self-Aligned SiGe p-MOS-MODFETs with SiN Gate DielectricLu, W. / Hammond, R. / Koester, S. / Wang, X. W. / Chu, J. C. / Ma, T. P. / Adesida, I. / IEEE et al. | 1999
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High-efficiency uni-traveling-carrier photodiode with an integrated total-reflection mirrorIto, H. / Furuta, T. / Kodama, S. / Ishibashi, T. et al. | 1999
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Improved ultraviolet quantum efficiency using a transparent recessed window AlGaN/GaN heterojunction p-i-n photodiodeLi, T. / Beck, A.L. / Collins, C. / Dupuis, R.D. / Campbell, J.C. / Schurman, M.J. / Ferguson, I.A. et al. | 1999
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Multiple-color GaAs/AlGaAs superlattice infrared photodetector controlled by the polarity and magnitude of the bias voltageHsu, M.C. / Kaun, C.H. / Wang, S.Y. / Lee, C.P. et al. | 1999
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Patterned 1.54mum Vertical Cavity Laser with Mismatched Defect-Free MirrorsQasaimeh, O. / Gebretsadik, H. / Bhattacharya, P. / Caneau, C. / Bhat, R. / IEEE et al. | 1999
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Patterned 1.54 /spl mu/m vertical cavity laser with mismatched defect-free mirrorsQasaimeh, O. / Gebretsadik, H. / Bhattacharya, P. / Caneau, C. / Bhat, R. et al. | 1999
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Mid-IR type-II interband cascade lasers based on InAs/GaInSb heterostructuresBradshaw, J.L. / Bruno, J.D. / Pham, J.T. / Wortman, D.E. / Yang, R.Q. et al. | 1999
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Mid-IR Type-II Interband Cascade Lasers Based on In As/GalnSb HeterostructuresBradshaw, J. / Bruno, J. / Pham, J. / Wortman, D. / Yang, R. / IEEE et al. | 1999
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Photon recycling semiconductor light emitting diodeXiaoyun Guo, / Schubert, E.F. et al. | 1999
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Advanced interconnect schemes towards 0.1 /spl mu/mMoussavi, M. et al. | 1999
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Advanced Interconnect Schemes Towards 0.1mum (Invited)Moussavi, M. / IEEE et al. | 1999
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Full-0.56 /spl mu/m pitch copper interconnects for a high performance 0.15-/spl mu/m CMOS logic deviceIguchi, M. / Takewaki, T. / Matsubara, Y. / Kunimune, Y. / Ito, N. / Tsuchiya, Y. / Matsui, T. / Fujii, K. / Motoyama, K. / Sugai, K. et al. | 1999
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Full-0.56mum Pitch Copper Interconnects for a High Performance 0.15mum CMOS Logic DeviceIguchi, M. / Takewaki, T. / Matsubara, Y. / Kunimune, Y. / Ito, N. / Tsuchiya, Y. / Matsui, T. / Fujii, K. / Motoyama, K. / Sugai, K. et al. | 1999
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0.5 mum Pitch Copper-Dual-Damascene Metallization Using Organic SOG (k=2.9) for 0.18-mum CMOS ApplicationsFukuda, T. / Ohshima, T. / Aoki, H. / Maruyama, H. / Miyazaki, H. / Konishi, N. / Fukada, S. / Yunogami, T. / Hotta, S. / Maekawa, S. et al. | 1999
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0.5-/spl mu/m-pitch copper-dual-damascene metallization using organic SOG (k=2.9) for 0.18-/spl mu/m CMOS applicationsFukuda, T. / Ohshima, T. / Aoki, H. / Maruyama, H. / Miyazaki, H. / Konishi, N. / Fukada, S. / Yunogami, T. / Hotta, S. / Maekawa, A. et al. | 1999
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Copper Dual Damascene Interconnects with Low-K (K~e~f~f<3.0) Dielectrics Using FLARE™ and an Organo-Silicate Hard MaskHasegawa, T. / Ikeda, K. / Tokunaga, K. / Yamamura, I. / Fukasawa, M. / Kito, H. / Miyata, K. / Komai, N. / Taguchi, M. / Hirano, S. et al. | 1999
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Copper dual damascene interconnects with low-K (K/sub eff/<3.0) dielectrics using FLARE/sup TM/ and an organo-silicate hard maskHasegawa, T. / Ikeda, K. / Tokunaga, K. / Yamamura, I. / Fukasawa, K. / Kito, H. / Miyata, K. / Komai, N. / Taguchi, M. / Hirano, S. et al. | 1999
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Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for 0.13mum CMOS DevicesOda, N. / Matsumoto, A. / Yokoyama, T. / Ishigami, T. / Motoyama, K. / Morita, N. / Aizawa, K. / Kishimoto, K. / Gomi, H. / IEEE et al. | 1999
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Chip-level performance improvement using triple damascene wiring design concept for 0.13 /spl mu/m CMOS devicesOda, N. / Matsumoto, A. / Yokoyama, T. / Ishigami, T. / Motoyama, K. / Morita, N. / Aizawa, K. / Kishimoto, R. / Gormi, H. et al. | 1999
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On-chip interconnect evaluation on delay time increase by crosstalkYamashita, K. / Odanaka, S. / Egashira, K. / Ueda, T. et al. | 1999
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Layered Ta-nitrides (LTN) barrier film by power swing sputtering (PSS) technique for MOCVD-Cu damascene interconnectsTagami, M. / Furuya, A. / Onodera, T. / Hayashi, Y. et al. | 1999
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CMOS Device Technology Toward 50 nm Region-Performance and Drain-Architecture (Invited)Hori, A. / Mizuno, B. / IEEE et al. | 1999
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CMOS device technology toward 50 nm region-performance and drain architectureHori, A. / Mizuno, B. et al. | 1999
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Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantationMiyashita, K. / Yoshimura, H. / Takayanagi, M. / Fujiwara, M. / Adachi, K. / Nakayama, T. / Toyoshima, Y. et al. | 1999
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An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDEMorifuji, E. / Ohishi, A. / Miyashita, K. / Kawashima, H. / Nakayama, T. / Yoshimura, H. / Toyoshima, Y. et al. | 1999
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50 nm gate-length CMOS transistor with super-halo: design, process, and reliabilityBin Yu, / Haihong Wang, / Milic, O. / Qi Xiang, / Weizhong Wang, / An, J.X. / Ming-Ren Lin, et al. | 1999
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Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate lengthSayama, H. / Nishida, Y. / Oda, H. / Oishi, T. / Shimizu, S. / Kunikiyo, T. / Sonoda, K. / Inoue, Y. / Inuishi, M. et al. | 1999
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Effect of (100) Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15um Gate LengthSayama, H. / Nishida, Y. / Oda, H. / Oishi, T. / Shimizu, S. / Kunikiyo, T. / Sonoda, K. / Inoue, Y. / Inuishi, M. / IEEE et al. | 1999
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Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ?Skotnicki, T. et al. | 1999
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A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structuresImai, K. / Yamaguchi, K. / Kimizuka, N. / Onishi, H. / Kudo, T. / Ono, A. / Noda, K. / Goto, Y. / Fujii, H. / Ikeda, M. et al. | 1999
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A 0.13mum CMOS Technology Integrating High-Speed and Low-Power/High-Density Devices with Two Different Well/Channel StructuresImai, K. / Yamaguchi, K. / Kimizuka, N. / Onishi, H. / Kudo, T. / Ono, A. / Noda, K. / Goto, Y. / Fujii, H. / Ikeda, M. et al. | 1999
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Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applicationsWu, C.C. / Diaz, C.H. / Lin, B.L. / Chang, S.Z. / Wang, C.C. / Liaw, J.J. / Wang, C.H. / Young, K.K. / Lee, K.H. / Liew, B.K. et al. | 1999
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Ultra-Low Leakage 0.16 mum CMOS for Low-Standby Power ApplicationsWu, C. C. / Diaz, C. / Lin, B. / Chang, S. Z. / Wang, C. C. / Liaw, J. J. / Wang, C. H. / Young, K. K. / Lee, K. H. / Liew, B. K. et al. | 1999
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A highly manufacturable 0.18 /spl mu/m generation logic technologyIkeda, S. / Yoshida, Y. / Shoji, K. / Kuroda, K. / Komori, K. / Suzuki, N. / Okuyama, K. / Kamohara, S. / Ishitsuka, N. / Miura, H. et al. | 1999
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A Highly Manufacturable 0.18mum Generation LOGIC TechnologyIkeda, S. / Yoshida, Y. / Shoji, K. / Kuroda, K. / Komori, K. / Suzuki, N. / Okuyama, K. / Kamohara, S. / Ishitsuka, N. / Miura, H. et al. | 1999
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High Performance 0.18mum SOI CMOS TechnologyLeobandung, E. / Barth, E. / Sherony, M. / Lo, S.-H. / Schulz, R. / Chu, W. / Khare, M. / Sadana, D. / Schepis, D. / Bolam, R. et al. | 1999
- 679
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High performance 0.18 /spl mu/m SOI CMOS technologyLeobandung, E. / Barth, E. / Sherony, M. / Lo, S.-H. / Schulz, R. / Chu, W. / Khare, M. / Sadana, D. / Schepis, D. / Boiam, R. et al. | 1999
- 683
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1 GHz microprocessor integration with high performance transistor and low RC delayJonghyon Ahn, / Hyun-Sik Kim, / Tae-Jin Kim, / Hyung-Ho Shin, / Young-Ho Kim, / Dong-Uk Lim, / Joon Kim, / Uin Chung, / Soo-Cheol Lee, / Kwang-Pyuk Suh, et al. | 1999
- 689
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Low actuation voltage RF MEMS switches with signal frequencies from 0.25 GHz to 40 GHzShyh-Chiang Shen, / Feng, M. et al. | 1999
- 693
-
A micro-electro-mechanically (MEM) switched microstrip ring resonatorChoudhury, D. / Foschaar, J.A. et al. | 1999
- 697
-
A low-voltage rotary actuator fabricated using a five-level polysilicon surface micromachining technologyKrygowski, T.W. / Rodgers, M.S. / Sniegowski, J. / Miller, S.M. / Jakubczak, J. et al. | 1999
- 701
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Surface/bulk micromachining (SBM) process and deep trench oxide isolation method for MEMSSangwoo Lee, / Sangjun Park, / Dong-Il Cho, / Yongsoo Oh, et al. | 1999
- 705
-
Very large current density from carbon nanotube field emittersZhu, W. / Bower, C. / Zhou, O. / Kochanski, G. / Jin, S. et al. | 1999
- 709
-
Co-Silicide Formation on Silicon FEAs from Co, Ti/Co and Co/Ti LayersShim, B. C. / Park, B.-G. / Lee, J. D. / IEEE et al. | 1999
- 709
-
Co-silicide formation on silicon FEAs from Co, Co/Ti and Ti/Co layersByung Chang Shim, / Byung-Gook Park, / Jong Duk Lee, et al. | 1999
- 715
-
An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisitedAlam, M.A. / Bude, J. / Weir, B. / Silverman, P. / Ghetti, A. / Monroe, D. / Cheung, K.P. / Moccio, S. et al. | 1999
- 719
-
A physics-based, unified gate-oxide breakdown modelCheung, K.P. et al. | 1999
- 723
-
Analysis of trap-assisted conduction mechanisms through silicon dioxide films using quantum yieldGhetti, A. / Alam, M.A. / Bude, J. / Monroe, D. / Sangiorgi, E. / Vaidya, H. et al. | 1999
- 727
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Monte Carlo simulation of quantum yields exceeding unity as a probe of high-energy hole scattering rates in SiKamakura, Y. / Kawashima, I. / Deguchi, K. / Taniguchi, K. et al. | 1999
- 731
-
Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradationGhetti, A. / Sangiorgi, E. / Bude, J. / Sorsch, T.W. / Weber, G. et al. | 1999
- 735
-
Direct tunneling current model for circuit simulationChang-Hoon Choi, / Kwang-Hoon Oh, / Jung-Suk Goo, / Zhiping Yu, / Dutton, R.W. et al. | 1999
- 741
-
A novel hot carrier mechanism: band-to-band tunneling hole induced bipolar hot electron (BBHBHE)Lin, F.R.-L. / Cheng-Hao Poe, / Ching-Pen Yeh, / Po-Hao Wu, / Ni, J. / Hsu, C.C.-H. et al. | 1999
- 745
-
Light emission from MOS tunnel diodesVersari, R. / Pieracci, A. / Bellutti, P. / Ricci, B. et al. | 1999
- 749
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Light emission and detection by metal oxide silicon tunneling diodesLiu, C.W. / Lee, M.H. / Lin, C.F. / Lin, I.C. / Liu, W.T. / Lin, H.H. et al. | 1999
- 753
-
Monolithic high-Q overhang inductors fabricated on silicon and glass substratesJun-Bo Yoon, / Chui-Hi Han, / Euisik Yoon, / Choong-Ki Kim, et al. | 1999
- 757
-
Integration of high-Q inductors in a latch-up resistant CMOS technologyFrei, M.R. / Belk, N.R. / Dennis, D.C. / Carroll, M.S. / Lin, W. / Pinto, M.R. / Archer, V.D. / Ivanov, T.G. / Moinian, S. / Ng, K.K. et al. | 1999
- 761
-
Reference SAW oscillator on quartz-on-silicon (QoS) wafer for polylithic integration of true single chip radioYunseong Eo, / Seokbong Hyun, / Pilsoon Choi, / Kwyro Lee, / Gilhwan Oh, / Joong-Won Lee, et al. | 1999
- 765
-
CoSi~2 Integrated Fuses on Poly Silicon for Low Voltage 0.18mum CMOS ApplicationsKalnitsky, A. / Saadat, I. / Bergemont, A. / Francis, P. / IEEE et al. | 1999
- 765
-
CoSi/sub 2/ integrated fuses on poly silicon for low voltage 0.18 /spl mu/m CMOS applicationsKalnitsky, A. / Saadat, I. / Bergemont, A. / Francis, P. et al. | 1999
- 771
-
InP-based high-speed electronicsNakajima, H. / Ishibashi, T. / Sano, E. / Ida, M. / Yamahata, S. / Ishii, Y. et al. | 1999
- 771
-
InP-Based High-Speed Electronics (Invited)Nakajima, H. / Ishibashi, T. / Sano, E. / Ida, M. / Yamahata, S. / Ishii, Y. / IEEE et al. | 1999
- 775
-
A DC-3 GHz cryogenic AlGaAs/GaAs HBT low noise MMIC amplifier with 0.15 dB noise figureKobayashi, K.W. / Fernandez, J.E. / Kobayashi, J.H. / Leung, M. / Oki, A.K. / Tran, L.T. / Lammert, M. / Block, T.R. / Streit, D.C. et al. | 1999
- 779
-
69 GHz frequency divider with a cantilevered base InP DHBTGutierrez-Aitken, A. / Kaneshiro, E. / Tang, B. / Notthoff, J. / Chin, P. / Streit, D. / Oki, A. et al. | 1999
- 783
-
Metamorphic In~0~.~5~2Al~0~.~4~8As/In~0~.~5~3Ga~0~.~4~7As HEMTs on GaAs Substrate with f~T Over 200 GHzDumka, D. / Hoke, W. / Lemonias, P. / Cueva, G. / Adesida, I. / IEEE et al. | 1999
- 783
-
Metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As HEMTs on GaAs substrate with f/sub T/ over 200 GHzDumka, D.C. / Hoke, W.E. / Lemonias, P.J. / Cueva, G. / Adesida, I. et al. | 1999
- 789
-
Low Temperature (Ba, Sr) TiO~3 Capacitor Process Integration (LTB) Technology for Gigabit Scaled DRAMsHieda, K. / Eguchi, K. / Nakahira, J. / Kiyotoshi, M. / Nakabayashi, M. / Tomita, H. / Izuha, M. / Aoyama, T. / Niwa, S. / Tsunoda, K. et al. | 1999
- 789
-
Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMsHieda, K. / Eguchi, K. / Nakahira, J. / Kiyotoshi, M. / Nakabayashi, M. / Tomita, H. / Izuha, M. / Aoyama, T. / Niwa, S. / Tsunoda, K. et al. | 1999
- 793
-
Development of Ru/Ta/sub 2/O/sub 5//Ru capacitor technology for giga-scale DRAMsJin-Won Kim, / Sang-Don Nam, / Seung-Hwan Lee, / Seok-Jun Won, / Wan-Don Kim, / Cha-Young Yoo, / Young-Wook Park, / Sang-In Lee, / Moon-Yong Lee, et al. | 1999
- 793
-
Development of Ru/Ta~2O~5/Ru Capacitor Technology for Giga-scale DRAMsKim, J.-W. / Nam, S.-D. / Lee, S.-H. / Won, S.-J. / Kim, W.-D. / Yoo, C.-Y. / Park, Y.-W. / Lee, S.-I. / Lee, M.-Y. / IEEE et al. | 1999
- 797
-
Advanced amorphous dielectrics for embedded capacitorsAlers, G.B. / van Dover, R.B. / Schneemeyer, L.F. / Stirling, L. / Sung, C.Y. / Diodato, P.W. / Liu, R. / Wong, Y.H. / Fleming, R.M. / Lang, D.V. et al. | 1999
- 797
-
Advanced Amorphous Dielectrics for Embedded Capacitors (Invited)Alers, G. / van Dover, R. / Schneemeyer, L. / Stirling, L. / Sung, C. Y. / Diodato, P. / Liu, R. / Wong, Y. H. / Fleming, R. / Lang, D. et al. | 1999
- 801
-
A hydrogen barrier interlayer dielectric with a SiO/sub 2//SiON/SiO/sub 2/ stacked film for logic-embedded FeRAMsNakura, T. / Mori, H. / Inoue, N. / Ikarashi, N. / Takahashi, S. / Kasai, N. et al. | 1999
- 801
-
A Hydrogen Barrier Interlayer Dielectric with a SiO~2/SiON/SiO~2 Stacked Film for Logic-Embedded FeRAMsNakura, T. / Mori, H. / Inoue, N. / Ikarashi, N. / Takahashi, S. / Kasai, N. / IEEE et al. | 1999
- 805
-
Advanced Thermally Stable Silicide S/D Electrodes for High-Speed Logic Circuits with Large-Scale Embedded Ta~2O~5-Capacitor DRAMsSaito, M. / Yoshida, M. / Asaka, K. / Goto, H. / Fukuda, N. / Kawano, M. / Kojima, M. / Suzuki, M. / Ogaya, K. / Enomoto, H. et al. | 1999
- 805
-
Advanced thermally stable silicide S/D electrodes for high-speed logic circuits with large-scale embedded Ta/sub 2/O/sub 5/-capacitor DRAMsSaito, M. / Yoshida, M. / Asaka, K. / Goto, H. / Fukuda, N. / Kawano, M. / Kojima, M. / Suzuki, M. / Ogaya, K. / Enomoto, H. et al. | 1999
- 809
-
Level-specific strategy of KrF microlithography for 130 nm DRAMsInoue, S. / Asano, M. / Hosaka, K. / Sutani, T. / Azuma, T. / Kawamura, D. / Kobayashi, M. / Miyoshi, S. / Kanemitsu, H. / Tanaka, S. et al. | 1999
- 815
-
Extraction of the Gate Oxide Thickness of N- and P-Channel MOSFETs Below 20Angstrom from the Substrate Current Resulting from Valence-Band Electron TunnelingShanware, A. / Shiely, J. / Massoud, H. / Vogel, E. / Henson, K. / Srivastava, A. / Osburn, C. / Hauser, J. / Wortman, J. / IEEE et al. | 1999
- 815
-
Extraction of the gate oxide thickness of N- and P-Channel MOSFETs below 20 /spl Aring/ from the substrate current resulting from valence-band electron tunnelingShanware, A. / Shiely, J.P. / Massoud, H.Z. / Vogel, E. / Henson, K. / Srivastava, A. / Osburn, C. / Hauser, J.R. / Wortman, J.J. et al. | 1999
- 819
-
Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel techniqueMomose, H.S. / Ohguro, T. / Morifuji, E. / Sugaya, H. / Nakamura, S. / Yoshitomi, T. / Kimijima, H. / Morimoto, T. / Matsuoka, F. / Katsumata, Y. et al. | 1999
- 819
-
Improvement of Direct-Tunneling Gate Leakage Current in Ultra-thin Gate Oxide CMOS with TiN Gate Electrode CMOS using Non-Doped Selective Epitaxial Si Channel TechniqueMomose, H. S. / Ohguro, T. / Morifuji, E. / Sugaya, H. / Nakamura, S. / Yoshitomi, T. / Kimijima, H. / Morimoto, T. / Matsuoka, F. / Katsumata, Y. et al. | 1999
- 823
-
Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxidesKubicek, S. / Henson, W.K. / De Keersgieter, A. / Badenes, G. / Jansen, P. / van Meer, H. / Kerr, D. / Naem, A. / Deferm, L. / De Meyer, K. et al. | 1999
- 827
-
NMOS drive current reduction caused by transistor layout and trench isolation induced stressScott, G. / Lutze, J. / Rubin, M. / Nouri, F. / Manley, M. et al. | 1999
- 831
-
Analysis and control of hysteresis in PD/SOI CMOSPelella, M.M. / Fossum, J.G. / Chiang, M.-H. / Workman, G.O. / Tretz, C.R. et al. | 1999
- 835
-
Actively Biased p-channel MOSFETs Studied with Scanning Capacitence MicroscopyNakakura, C. / Hetherington, D. / Shaneyfelt, M. / Dodd, P. / De Wolf, P. / IEEE et al. | 1999
- 835
-
Actively biased p-channel MOSFET studied with scanning capacitance microscopyNakakura, C.Y. / Hetherington, D.L. / Shaneyfelt, M.R. / Dodd, P.E. / De Wolf, P. et al. | 1999
- 839
-
1/f noise characterization of deep sub-micron dual thickness nitrided gate oxide n- and p-MOSFETsD'Souza, S. / Li-Ming Hwang, / Matloubian, M. / Martin, S. / Sherman, P. / Joshi, A. / Hong Wu, / Bhattacharya, S. / Kempf, P. et al. | 1999
- 845
-
Integration and Design Issues in Combining Very-High-Speed Silicon-Germanium Bipolar Transistors and ULSI CMOS for System-on-a-Chip Applications (Invited)Subbanna, S. / Freeman, G. / Ahlgren, D. / Greenberg, D. / Harame, D. / Dunn, J. / Herman, D. / Meyerson, B. / Greshishchev, Y. / Schvan, P. et al. | 1999
- 845
-
Integration and design issues in combining very-high-speed silicon-germanium bipolar transistors and ULSI CMOS for system-on-a-chip applicationsSubbanna, S. / Freeman, G. / Ahlgren, D. / Greenberg, D. / Harame, D. / Dunn, J. / Herman, D. / Meyerson, B. / Greshishchev, Y. / Schvan, P. et al. | 1999
- 849
-
"System on a Chip" Technology Platform for 0.18mum Digital, Mixed Signal & eDRAM ApplicationsMahnkopf, R. / Allers, K.-H. / Armacost, M. / Augustin, A. / Barth, J. / Brase, G. / Busch, R. / Demm, E. / Dietz, G. / Flietner, B. et al. | 1999
- 849
-
'System on a chip' technology platform for 0.18 /spl mu/m digital, mixed signal and eDRAM applicationsMahnkopf, R. / Allers, K.-H. / Armacost, M. / Augustin, A. / Barth, J. / Brase, G. / Busch, R. / Demm, E. / Dietz, G. / Flietner, B. et al. | 1999
- 853
-
RF potential of a 0.18-/spl mu/m CMOS logic technologyBurghartz, J.N. / Hargrove, M. / Webster, C. / Groves, R. / Keenes, M. / Jenkins, K. / Edelstein, D. / Logan, R. / Nowak, E. et al. | 1999
- 853
-
RF Potential of a 0.18mum CMOS Logic TechnologyBurghartz, J. / Hargrove, M. / Webster, C. / Groves, R. / Keene, M. / Jenkins, K. / Edelstein, D. / Logan, R. / Nowak, E. / IEEE et al. | 1999
- 857
-
A 0.16mum Modular BiCMOS (COM2-BiCMOS) Technology for RF Communication ICsCarroll, M. / Ivanov, T. / Chyan, Y.-F. / Nguyen, D. / Huang, C. / Hsu, T.-I. / Leung, C. W. / Cochran, W. / IEEE et al. | 1999
- 857
-
A 0.16 /spl mu/m modular BiCMOS (COM2-BiCMOS) technology for RF communication ICsCarroll, M.S. / Ivanov, T.G. / Yih-Feng Chyan, / Nguyen, D.P. / Chunchieh Huang, / Ting-Ih Hsu, / Chung Wai Leung, / Cochran, W.T. et al. | 1999
- 861
-
Impact of interconnect capacitance reduction on RF-Si device performanceNakahara, Y. / Yano, H. / Suzuki, Y. / Furukawa, A. et al. | 1999
- 867
-
Performance limits in visible and infrared imager sensorsKozlowski, L.J. / Luo, J. / Tomasini, A. et al. | 1999
- 867
-
Performance Limits in Visible and Infrared Imager Sensors (Invited)Kozlowski, L. / Luo, J. / Tomasini, A. / IEEE et al. | 1999
- 871
-
A low dark current double membrane poly-Si FT-technology for 2/3 inch 6M pixel CCD imagersPeek, H.L. / Verbugt, W.E. / Heijns, H. et al. | 1999
- 875
-
A high speed CMOS imager acquiring 5000 frames/secLauxtermann, S. / Schwider, P. / Bloss, H. / Ernst, J. / Firla, H. et al. | 1999
- 879
-
Intelligent image sensor chip with three dimensional structureKurino, H. / Lee, K.W. / Nakamura, T. / Sakuma, K. / Park, K.T. / Miyakawa, N. / Shimazutsu, H. / Kim, K.Y. / Inamura, K. / Koyanagi, M. et al. | 1999
- 883
-
New LV-BPD (low voltage buried photo-diode) for CMOS imagerInoue, I. / Nozaki, H. / Yamashita, H. / Yamaguchi, T. / Ishiwata, H. / Ihara, H. / Miyagawa, R. / Miura, H. / Nakamura, N. / Egawa, Y. et al. | 1999
- 887
-
A new sensor structure and fabrication process for a single-chip fingerprint sensor/identifier LSIMachida, K. / Shigematsu, S. / Morimura, H. / Shimoyama, N. / Tanabe, Y. / Kumazaki, T. / Kudou, K. / Yano, M. / Kyuragi, H. et al. | 1999
- 893
-
A fast and accurate computation of interconnect capacitancePutot, S. / Charlet, F. / Witomski, P. et al. | 1999
- 897
-
Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meterFroment, B. / Paillardet, F. / Bely, M. / Cluzel, J. / Granger, E. / Haond, M. / Dugoujon, L. et al. | 1999
- 897
-
Ultra Low Capacitance Measurements in Multilevel Metallization CMOS by Using a Built-In Electron-MeterFroment, B. / Paillardet, F. / Bely, M. / Cluzel, J. / Granger, E. / Haond, M. / Dugougeon, L. / IEEE et al. | 1999
- 901
-
Line inductance extraction and modeling in a real chip with power gridKleveland, B. / Xiaoning Qi, / Madden, L. / Dutton, R.W. / Wong, S.S. et al. | 1999
- 905
-
Characterization of Crosstalk-Induced Noise for 0.18mum CMOS Technology with 6-level Metallization Using Time Domain Reflectometry and S-ParametersLee, H.-D. / Jang, M.-J. / Kang, D.-G. / Hwang, J.-M. / Kim, Y.-J. / Kwon, O.-K. / Kim, D.-M. / IEEE et al. | 1999
- 905
-
Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parametersHi-Deok Lee, / Myoung-Jun Jang, / Dae-Gwan Kang, / Jeong-Mo Hwang, / Yong-Joo Kim, / Oh-Kyong Kwon, / Dae-Mann Kim, et al. | 1999
- 909
-
A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD filmsTat-Kwan Yu, / Chheda, S. / Ko, J. / Roberton, M. / Dengi, A. / Travis, E. et al. | 1999
- 913
-
A novel approach to simulate the effect of optical proximity on MOSFET parametric yieldBalasinski, A. / Gangala, H. / Axelrad, V. / Boksha, V. et al. | 1999
- 919
-
Fabrication, Characterization and Self-Consistent Simulation of an SOI Nano Flash Memory DeviceTang, X. / Baie, X. / Bayot, V. / Van de Wiele, F. / Colinge, J. / IEEE et al. | 1999
- 919
-
Ultra-thin body SOI MOSFET for deep-sub-tenth micron eraYang-Kyu Choi, / Asano, K. / Lindert, N. / Subramanian, V. / Tsu-Jae King, / Bokor, J. / Chenming Hu, et al. | 1999
- 922
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A Direct Tunneling Memory (DTM) utilizing novel floating gate structureHoriguchi, N. / Usuki, T. / Goto, K. / Futatsugi, T. / Sugii, T. / Yokoyama, N. et al. | 1999
- 925
-
High Al-content AlGaN/GaN HEMTs on SiC substrates with very high power performanceWu, Y.-F. / Kapolnek, D. / Ibbetson, J. / Zhang, N.-Q. / Parikh, P. / Keller, B.P. / Mishra, U.K. et al. | 1999
- 928
-
Very high performance 50 nm CMOS at low temperatureWind, S.J. / Shi, L. / Lee, K.-L. / Roy, R.A. / Zhang, Y. / Sikorski, E. / Kozlowski, P. / D'emic, C. / Bucchignano, J.J. / Wann, H.-J. et al. | 1999
- 931
-
Ultra-low contact resistance for deca-nm MOSFETs by laser annealingGoto, K. / Yamamoto, T. / Kubo, T. / Kase, M. / Yun Wang, / Tengshing Lin, / Talwar, S. / Sugii, T. et al. | 1999
- 934
-
High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technologyMizuno, T. / Takagi, S. / Sugiyama, N. / Koga, J. / Tezuka, T. / Usuda, K. / Hatakeyama, T. / Kurobe, A. / Toriumi, A. et al. | 1999
- 937
-
0.1mum CMOS Technology for High-Speed Logic and System LSIs with SiO/SiN/poly-Si/W Gate SystemOnai, T. / Tsujikawa, S. / Uchino, T. / Tsuchiya, R. / Ohnishi, K. / Fukuda, H. / Hisamoto, D. / Yamamoto, N. / Yugami, J. / Ichinose, R. et al. | 1999
- 937
-
0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-systemOnai, T. / Tsujikawa, S. / Uchino, T. / Tsuchiya, R. / Ohnishi, K. / Fukuda, H. / Hisamoto, D. / Yamamoto, N. / Yugami, J. / Ichinose, K. et al. | 1999
- 940
-
Electrical properties of submicron (/spl ges/0.13 /spl mu/m/sup 2/) Ir/PZT/Ir capacitors formed on W plugsMoise, T.S. / Summerfelt, S.R. / Xing, G. / Colombo, L. / Sakoda, T. / Gilbert, S.R. / Loke, A. / Ma, S. / Kavari, R. / Wills, L.A. et al. | 1999
- 940
-
Electrical Properties of Submicron (>or=0.13mum^2) Ir/PZT/Ir Capacitors Formed on W PlugsMoise, T. / Summerfelt, S. / Xing, G. / Colombo, L. / Sakoda, T. / Gilbert, S. / Loke, A. / Ma, S. / Kavari, R. / Wills, L. et al. | 1999