Implementation of a Configurable Controller for an AC Drive Control: A Case Study (English)
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- New search for: Bikfalvi, P.
- New search for: Nedevschi, S.
- New search for: Vasarhelyi, J.
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- New search for: Imecs, M.
- New search for: Bikfalvi, P.
- New search for: Nedevschi, S.
- New search for: Vasarhelyi, J.
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In:
Field-programmable custom computing machines
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323-324
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2000
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Implementation of a Configurable Controller for an AC Drive Control: A Case Study
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Contributors:Imecs, M. ( author ) / Bikfalvi, P. ( author ) / Nedevschi, S. ( author ) / Vasarhelyi, J. ( author ) / Hutchings, B. L. / IEEE
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Conference:Symposium, Field-programmable custom computing machines ; 2000 ; Napa Valley, CA
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Published in:
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Publisher:
- New search for: IEEE Computer Society
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Publication date:2000-01-01
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Size:2 pages
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Remarks:IEEE Cat no PR00871
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
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Design of a VLIW compute accelerator on the Transmogrifier-2Zhang, L.L. / Wang, Q. / Lewis, D.M. et al. | 2000
- 13
-
A scalable, loadable custom programmable logic device for solving Boolean satisfiability problemsBoyd, M.J. / Larrabee, T. et al. | 2000
- 22
-
Configuration caching management techniques for reconfigurable computingLi, Z. / Compton, K. / Hauck, S. et al. | 2000
- 39
-
A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systemsBanerjee, P. / Shenoy, N. / Choudhary, A. / Hauck, S. / Bachmann, C. / Haldar, M. / Joisha, P. / Jones, A. / Kanhare, A. / Nayak, A. et al. | 2000
- 49
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Stream-oriented FPGA computing in the Streams-C high level languageGokhale, M. / Stone, J. / Arnold, J. / Kalinowski, M. et al. | 2000
- 59
-
A reconfigurable computing architecture for microsensorsScalera, S. / Falco, M. / Nelson, B. et al. | 2000
- 68
-
FPGA implementation of a microcoded elliptic curve cryptographic processorLeung, K.H. / Ma, K.W. / Wong, W.K. / Leong, P.H.W. et al. | 2000
- 77
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Customising graphics applications: techniques and programming interfaceStyles, H. / Luk, W. et al. | 2000
- 77
-
Customizing Graphics Applications: Techniques and Programming InterfaceStyles, H. / Luk, W. / IEEE et al. | 2000
- 91
-
Automatic synthesis of data storage and control structures for FPGA-based computing enginesDiniz, P. / Park, J. et al. | 2000
- 101
-
A C to HDL compiler for pipeline processing on FPGAsMaruyama, T. / Hoshino, T. et al. | 2000
- 113
-
High Performance DES Encryption in Virtex™ FPGAs Using Jbits™Patterson, C. / IEEE et al. | 2000
- 113
-
High performance DES encryption in Virtex/sup TM/ FPGAs using JBits/sup TM/Patterson, C. et al. | 2000
- 122
-
A bit-serial implementation of the international data encryption algorithm IDEALeong, M.P. / Cheung, O.Y.H. / Tsoi, K.H. / Leong, P.H.W. et al. | 2000
- 132
-
An adaptive cryptographic engine for IPSec architecturesDandalis, A. / Prasanna, V.K. / Rolim, J.D.P. et al. | 2000
- 145
-
Death of the RLOC?Singh, S. et al. | 2000
- 153
-
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device ConfigurationsJames-Roxby, P. / Guccione, S. / IEEE et al. | 2000
- 153
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Automated extraction of run-time parameterisable cores from programmable device configurationsJames-Roxby, P. / Guccione, S.A. et al. | 2000
- 165
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Dynamic fault tolerance in FPGAs via partial reconfigurationEmmert, J. / Stroud, C. / Skaggs, B. / Abramovici, M. et al. | 2000
- 175
-
An ACS robotic control algorithm with fault tolerant capabilitiesYu, S.-Y. / Saxena, N. / McCluskey, E.J. et al. | 2000
- 185
-
Tunable fault tolerance for runtime reconfigurable architecturesSinha, S.K. / Kamarchik, P.M. / Goldstein, S.C. et al. | 2000
- 195
-
Synchronization in software radios. Carrier and timing recovery using FPGAsDick, C. / Harris, F. / Rice, M. et al. | 2000
- 205
-
Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systemsAlsolaim, A. / Becker, J. / Glesner, M. / Starzyk, J. et al. | 2000
- 217
-
Implementation of near Shannon limit error-correcting codes using reconfigurable hardwareLevine, B. / Reed Taylor, R. / Schmit, H. et al. | 2000
- 227
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Hardware-software codesign and parallel implementation of a Golomb ruler derivation engineSotiriades, E. / Dollas, A. / Athanas, P. et al. | 2000
- 236
-
An FPGA-based coprocessor for the parsing of context-free grammarsCiressan, C. / Sanchez, E. / Rajman, M. / Chappelier, J.-C. et al. | 2000
- 249
-
A reliable LZ data compressor on reconfigurable coprocessorsHuang, W.-J. / Saxena, N. / McCluskey, E.J. et al. | 2000
- 259
-
EVIDENCE: an FPGA-based system for photon event identification and centroidingAlderighi, M. / D'Angelo, S. / Sechi, G.R. et al. | 2000
- 267
-
Improving the performance and efficiency of an adaptive amplification operation using configurable hardwareWirthlin, M.J. / Morrison, S. / Graham, P. / Bray, B. et al. | 2000
- 279
-
Configuration relocation and defragmentation for reconfigurable computingCompton, K. / Cooley, J. / Knol, S. / Hauck, S. et al. | 2000
- 281
-
Mapping algorithms for a multi-bit data path processing reconfigurable chip RHWYamauchi, T. / Nakaya, S. / Inuo, T. / Kajihara, N. et al. | 2000
- 283
-
Hardware accelerator for subgraph isomorphism problemsIchikawa, S. / Udorn, L. / Konishi, K. et al. | 2000
- 285
-
A reconfigurable hardware platform for digital real-time signal processing in television studiosHenriss, K. / Ruffer, P. / Ernst, R. / Hasenzahl, S. et al. | 2000
- 287
-
Reconfigurable array media processor (RAMP)Rath, K. / Tangirala, S. / Friel, P. / Balsara, P. / Flores, J. / Wadley, J. et al. | 2000
- 289
-
Internet connected FPGAsFallside, H. / John, M. / Smith, S. et al. | 2000
- 291
-
A reconfigurable stochastic model simulator for analysis of parallel systemsYamamoto, O. / Shibata, Y. / Kurosawa, H. / Amano, H. et al. | 2000
- 295
-
A virtual hardware system on a dynamically reconfigurable logic deviceShibata, Y. / Uno, M. / Amano, H. / Furuta, K. / Fujii, T. / Motomura, M. et al. | 2000
- 297
-
Optimal vs. heuristic approaches to context scheduling for multi-context reconfigurable architecturesMaestre, R. / Kurdahi, F.J. / Femandez, M. / Hermida, R. / Bagherzadeh, N. / Singh, H. et al. | 2000
- 299
-
A communication scheduling algorithm for multi-FPGA systemsJinwoo Suh, / Dong-In Kang, / Crago, S.P. et al. | 2000
- 301
-
Preemptive multitasking on FPGAsLevinson, L. / Manner, R. / Sessler, M. / Simmler, H. et al. | 2000
- 303
-
BigSky - an on-line arithmetic design tool for FPGAsSchneider, A. / McIlhenny, R. / Ercegevac, M.D. et al. | 2000
- 305
-
Improving the FPGA design process through determining and applying logical-to-physical design mappingsGraham, P. / Hutchings, B. / Nelson, B. et al. | 2000
- 307
-
Multiple precision for resource minimizationConstantinides, G.A. / Cheung, P.Y.K. / Luk, W. et al. | 2000
- 309
-
StReAm: object-oriented programming of stream architectures using PAM-BloxMencer, O. / Hubert, H. / Morf, M. / Flynn, M.J. et al. | 2000
- 313
-
An FPGA-based array processor for an ionospheric-imaging radarTuan, T. / Figueroa, M. / Lind, F. / Zhou, C. / Diorio, C. / Sahr, J. et al. | 2000
- 315
-
Embedded compilation for multimedia applicationsDaw, N. / Goldstein, S. / Strelow, D. et al. | 2000
- 317
-
Interfacing reconfigurable logic with a CPUWalker, K. / Budiu, M. / Goldstein, S.C. et al. | 2000
- 319
-
A run-time reconfigurable plug-in for the Winamp MP3 playerScalera, J. / Jones, M. et al. | 2000
- 321
-
Accelerating embedded applications using dynamically reconfigurable hardware and evolutionary algorithmsHarkin, J. / McGinnity, T.M. / Maguire, L.P. et al. | 2000
- 323
-
Implementation of a configurable controller for an AC drive control: a case studyImecs, M. / Bikfalvi, P. / Nedevschi, S. / Vasarhelyi, J. et al. | 2000
- 325
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Pattern recognition and reconstruction on a FPGA coprocessor boardManner, R. / Sessler, M. / Simmler, H. et al. | 2000
- 325
-
Pattern Recognition and Reconstruction on an FPGA Coprocessor BoardManner, R. / Sessler, M. / Simmler, H. / IEEE et al. | 2000
- 329
-
FCCMs and the memory wallDerrien, S. / Rajopadhye, S. et al. | 2000
- 331
-
A C to hardware/software compilerBazargan, K. / Kastner, R. / Ogrenci, S. / Sarrafzadeh, M. et al. | 2000
- 333
-
Evaluating hardware compilation techniquesWeinhardt, M. / Luk, W. et al. | 2000
- 335
-
Adapting constant multipliers in a neural network implementationJames-Roxby, P. / Blodget, B.A. et al. | 2000
- 337
-
A networked FPGA-based hardware implementation of a neural network applicationRestrepo, H.F. / Hoffmann, R. / Perez-Uribe, A. / Teuscher, C. / Sanchez, E. et al. | 2000
- 339
-
Design of C++ class library and bit-serial compiler for variable-precision datapath synthesis on adaptive computing systemsSuzuki, K. / Wang, M.X. / Fang Zhao, / Dai, W.W.-M. et al. | 2000
- 341
-
An investigation of reconfigurable multipliers for use in adaptive signal processingCourtney, T. / Turner, R. / Woods, R. et al. | 2000
- 344
-
Combining Serialization and Reconfiguration for Convolver DesignsDerbyshire, A. / Luk, W. / IEEE et al. | 2000
- 344
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Combining serialisation and reconfiguration for convolver designsDerbyshire, A. / Luk, W. et al. | 2000
- 347
-
Author index| 2000
- iii
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Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)| 2000