A Pipelined Memory Architecture for High Throughput Network Processors (English)
- New search for: Sherwood, T.
- New search for: Varghese, G.
- New search for: Calder, B.
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- New search for: Sherwood, T.
- New search for: Varghese, G.
- New search for: Calder, B.
- New search for: IEEE
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In:
Computer architecture
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288-299
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2003
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ISBN:
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ISSN:
- Conference paper / Print
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Title:A Pipelined Memory Architecture for High Throughput Network Processors
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Contributors:
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Conference:Annual International symposium; 30th, Computer architecture ; 2003 ; San Diego, CA
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Published in:Computer architecture ; 288-299
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Publisher:
- New search for: IEEE Computer Society
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Publication date:2003-01-01
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Size:12 pages
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Remarks:Also known as ISCA 2003
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2
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Temperature-aware microarchitectureSkadron, K. / Stan, M.R. / Huang, W. / Sivakumar Velusamy, / Karthik Sankaranarayanan, / Tarjan, D. et al. | 2003
- 14
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Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessorMagklis, G. / Scott, M.L. / Semeraro, G. / Albonesi, D.H. / Dropsho, S. et al. | 2003
- 28
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Half-price architectureIlhyun Kim, / Lipasti, M.H. et al. | 2003
- 39
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Implicitly-multithreaded processorsIl Park, / Falsafi, B. / Vijaykumar, T.N. et al. | 2003
- 52
-
MisSPECulation: partial and misleading use of spec CPU2000 in computer architecture conferencesCitron, D. et al. | 2003
- 62
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Banked multiported register files for high-frequency superscalar microprocessorsTseng, J.H. / Asanovic, K. et al. | 2003
- 72
-
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltagePowell, M.D. / Vijaykumar, T.N. et al. | 2003
- 84
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SMARTS: accelerating microarchitecture simulation via rigorous statistical samplingWunderlich, R.E. / Wenisch, T.F. / Falsafi, B. / Hoe, J.C. et al. | 2003
- 98
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Transient-fault recovery for chip multiprocessorsGomaa, M. / Scarbrough, C. / Vijaykumar, T.N. / Pomeranz, I. et al. | 2003
- 110
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ReEnact: using thread-level speculation mechanisms to debug data races in multithreaded codesPrvulovic, M. / Torrellas, J. et al. | 2003
- 122
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A "flight data recorder" for enabling full-system multiprocessor deterministic replayXu, M. / Bodik, R. / Hill, M.D. et al. | 2003
- 136
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A highly configurable cache architecture for embedded systemsZhang, C. / Vahid, F. / Najjar, W. et al. | 2003
- 147
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Energy efficient co-adaptive instruction fetch and issueBuyuktosunoglu, A. / Karkhanis, T. / Albonesi, D.H. / Pradip Bose, et al. | 2003
- 157
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Positional adaptation of processors: application to energy reductionHuang, M.C. / Renau, J. / Torrellas, J. et al. | 2003
- 169
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DRPM: dynamic speed control for power management in server class disksGurumurthi, S. / Sivasubramaniam, A. / Kandemir, M. / Franke, H. et al. | 2003
- 182
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Token Coherence: decoupling performance and correctnessMartin, M.M.K. / Hill, M.D. / Wood, D.A. et al. | 2003
- 194
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GOAL: a load-balanced adaptive routing algorithm for torus networksArjun Singh, / Dally, W.J. / Gupta, A.K. / Towles, B. et al. | 2003
- 206
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Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessorsMartin, M.M.K. / Harper, P.J. / Sorin, D.J. / Hill, M.D. / Wood, D.A. et al. | 2003
- 218
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Performance analysis of the Alpha 21364-based HP GS1280 multiprocessorCvetanovic, Z. et al. | 2003
- 230
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Parallelism in the front-endOberoi, P.S. / Sohi, G.S. et al. | 2003
- 241
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Effective ahead pipelining of instruction block address generationSeznec, A. / Fraboulet, A. et al. | 2003
- 253
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Cyclone: a broadcast-free dynamic instruction scheduler with selective replayErnst, D. / Hamel, A. / Austin, T. et al. | 2003
- 264
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Improving dynamic cluster assignment for clustered trace cache processorsRavi Bhargava, / John, L.K. et al. | 2003
- 275
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Dynamically managing the communication-parallelism trade-off in future clustered processorsRajeev Balasubramonian, / Sandhya Dwarkadas, / Albonesi, D.H. et al. | 2003
- 288
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A pipelined memory architecture for high throughput network processorsSherwood, T. / Varghese, G. / Calder, B. et al. | 2003
- 300
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Efficient use of memory bandwidth to improve network processor throughputJahangir Hasan, / Satish Chandra, / Vijaykumar, T.N. et al. | 2003
- 314
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Improving branch prediction by dynamic data flow-based identification of correlated branches from a large global historyThomas, R. / Franklin, M. / Wilkerson, C. / Stark, J. et al. | 2003
- 324
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Detecting global stride locality in value streamsHuiyang Zhou, / Flanagan, J. / Conte, T.M. et al. | 2003
- 336
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Phase tracking and predictionSherwood, T. / Sair, S. / Calder, B. et al. | 2003
- 350
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Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systemsAravindh Anantaraman, / Kiran Seth, / Kaustubh Patil, / Rotenberg, E. / Mueller, F. et al. | 2003
- 362
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DISE: a programmable macro engine for customizing applicationsCorliss, M.L. / Lewis, E.C. / Roth, A. et al. | 2003
- 374
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Building quantum wires: the long and the short of itOskin, M. / Chong, F.T. / Chuang, I.L. / Kubiatowicz, J. et al. | 2003
- 388
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Guided region prefetching: a cooperative hardware/software approachZhenlin Wang, / Burger, D. / McKinley, K.S. / Reinhardt, S.K. / Weems, C.C. et al. | 2003
- 399
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Overcoming the limitations of conventional vector processorsKozyrakis, C. / Patterson, D. et al. | 2003
- 410
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A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernelsSuh, J. / Kim, E.-G. / Crago, S.P. / Lakshmi Srinivasan, / French, M.C. et al. | 2003
- 422
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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architectureSankaralingam, K. / Nagarajan, R. / Haiming Liu, / Changkyu Kim, / Jaehyuk Huh, / Burger, D. / Keckler, S.W. / Moore, C.R. et al. | 2003
- 434
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The Jrpm system for dynamically parallelizing Java programsChen, M.K. / Olukotun, K. et al. | 2003
- 447
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Author index| 2003
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Proceedings 30th Annual International Symposium on Computer Architecture| 2003