SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator (English)
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In:
Asia-Pacific computer systems architecture conference; Advances in computer systems architecture, ACSAC 2003
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122-136
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2003
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ISBN:
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ISSN:
- Conference paper / Print
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Title:SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator
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Contributors:
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Conference:8th, Asia-Pacific computer systems architecture conference; Advances in computer systems architecture, ACSAC 2003 ; 2003 ; Aizu-Wakamatsu, Japan
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Published in:LECTURE NOTES IN COMPUTER SCIENCE ; 122-136
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Publisher:
- New search for: Springer-Verlag
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Place of publication:New York
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Publication date:2003-01-01
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Size:15 pages
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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How Can the Earth Simulator Impact on Human ActivitiesSato, T. / Murai, H. / Kitawaki, S. et al. | 2003
- 8
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Toward Architecting and Designing Novel ComputersNakamura, T. et al. | 2003
- 14
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Designing Ultra-large Instruction Issue WindowsBurger, D. et al. | 2003
- 21
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Multi-threaded Microprocessors - Evolution or RevolutionJesshope, C. et al. | 2003
- 46
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The Development of System Software for Parallel SupercomputersKorneev, V. et al. | 2003
- 54
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Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCAOguri, K. / Shibata, Y. / Nagoya, A. et al. | 2003
- 69
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Reconfigurable Logic: A Saviour for Experimental Computer Architecture ResearchMorris, J. et al. | 2003
- 86
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Design and Implementation of Java ProcessorsOmondi, A. R. et al. | 2003
- 97
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MOOSS: CPU Architecture with Memory Protection and Support for OOPBallner, R. / Tvrdik, P. et al. | 2003
- 112
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Reducing Access Count to Register-Files through Operand ReuseTakamura, H. / Inoue, K. / Moshnyaga, V. G. et al. | 2003
- 122
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SimAlpha Version 1.0: Simple and Readable Alpha Processor SimulatorKise, K. / Honda, H. / Yuba, T. et al. | 2003
- 137
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Towards an Asynchronous MIPS ProcessorZhang, Q. / Theodoropoulos, G. et al. | 2003
- 151
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On Implementing High Level Concurrency in JavaItzstein, G. S. / Jasiunas, M. et al. | 2003
- 166
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Simultaneous MultiStreaming for Complexity-Effective VLIW ArchitecturesRao, H. P. / Nandy, S. K. / Kiran, M. N. V. S. et al. | 2003
- 180
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A Novel Architecture for Genomic Sequence Searching and AlignmentGardner-Stephen, P. / Knowles, G. et al. | 2003
- 193
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A Reconfigurable Multi-threaded Architecture ModelWallner, S. et al. | 2003
- 208
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Reconfigurable Instruction-Level Parallel Processor ArchitectureIto, T. / Ono, K. / Ichikawa, M. / Okuyama, Y. / Kuroda, K. et al. | 2003
- 221
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Mapping Applications to a Coarse Grain Reconfigurable SystemGuo, Y. / Smit, G. J. M. / Broersma, H. / Rosien, M. A. J. / Heysters, P. M. et al. | 2003
- 236
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Packing with Boundary Constraints for a Reconfigurable Operating SystemSharma, A. / George, M. A. / Kearney, D. et al. | 2003
- 246
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Arithmetic Circuits Combining Residue and Signed-Digit RepresentationsLindstrom, A. / Nordseth, M. / Bengtsson, L. / Omondi, A. et al. | 2003
- 258
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A New On-the-fly Summation AlgorithmNikmehr, H. / Lim, C.-C. et al. | 2003
- 268
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State Reordering for Low Power Combinational LogicTsai, K.-L. / Lai, F. / Ruan, S.-J. / Chaung, S.-W. et al. | 2003
- 277
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User-Level Management of Kernel MemoryHaeberlen, A. / Elphinstone, K. et al. | 2003
- 290
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Variable Radix Page Table: A Page Table for Modern ArchitecturesSzmajda, C. / Heiser, G. et al. | 2003
- 305
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L1 Cache and TLB Enhancements to the RAMpage Memory HierarchyMachanick, P. / Patel, Z. et al. | 2003
- 320
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Legba: Fast Hardware Support for Fine-Grained ProtectionWiggins, A. / Winwood, S. / Tuch, H. / Heiser, G. et al. | 2003
- 337
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Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache SubsystemKabadi, M. G. / Parthasarathi, R. et al. | 2003
- 352
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Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM ProcessorWiggins, A. / Tuch, H. / Uhlig, V. / Heiser, G. et al. | 2003
- 365
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Performance of the Achilles RouterTham, S. / Morris, J. et al. | 2003
- 380
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Latency Improvement in Virtual MulticastingMachanick, P. / Andrew, B. et al. | 2003
- 395
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A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc NetworksIslam, M. M. / Pose, R. / Kopp, C. et al. | 2003