Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface (English)
- New search for: Ammendola, Roberto
- New search for: Biagionil, Andrea
- New search for: Frezza, Ottorino
- New search for: Cicero, Francesca Lo
- New search for: Lonardo, Alessandro
- New search for: Paolucci, Pier Stanislao
- New search for: Rossetti, Davide
- New search for: Simula, Francesco
- New search for: Tosoratto, Laura
- New search for: Vicini, Piero
- New search for: Ammendola, Roberto
- New search for: Biagionil, Andrea
- New search for: Frezza, Ottorino
- New search for: Cicero, Francesca Lo
- New search for: Lonardo, Alessandro
- New search for: Paolucci, Pier Stanislao
- New search for: Rossetti, Davide
- New search for: Simula, Francesco
- New search for: Tosoratto, Laura
- New search for: Vicini, Piero
- Conference paper / Electronic Resource
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Title:Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface
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Contributors:Ammendola, Roberto ( author ) / Biagionil, Andrea ( author ) / Frezza, Ottorino ( author ) / Cicero, Francesca Lo ( author ) / Lonardo, Alessandro ( author ) / Paolucci, Pier Stanislao ( author ) / Rossetti, Davide ( author ) / Simula, Francesco ( author ) / Tosoratto, Laura ( author ) / Vicini, Piero ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2013-12-01
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Size:1976688 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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Program Committee| 2013
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Automated design flow for no-cost configuration error detection in sram-based FPGAsBen Jrad, M. / Leveugle, R. et al. | 2013
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Energy-efficient large-scale matrix multiplication on FPGAsMatam, Kiran Kumar / Prasanna, Viktor K. et al. | 2013
- 1
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A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systemsRueckauer, Michael / Munoz, Daniel M. / Stripf, Timo / Oey, Oliver / Llanos, Carlos H. / Becker, Juergen et al. | 2013
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Improved method for parallel AES-GCM cores using FPGAsAbdellatif, Karim M. / Chotin-Avot, R. / Mehrez, H. et al. | 2013
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Mixed-grained reconfigurable architecture supporting flexible reliability and C-based designKonoura, Hiroaki / Alnajjar, Dawood / Mitsuyama, Yukio / Ochi, Hiroyuki / Imagawa, Takashi / Noda, Shinichi / Wakabayashi, Kazutoshi / Hashimoto, Masanori / Onoye, Takao et al. | 2013
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New universal element with integrated PUF and TRNG capabilityVarchola, Michal / Drutarovsky, Milos / Fischer, Viktor et al. | 2013
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Programming FPGA based NoCs with JavaPlumbridge, Gary / Audsley, Neil C. et al. | 2013
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Very low resource table-based FPGA evaluation of elementary functionsNeto, Horacio C. / Vestias, Mario P. et al. | 2013
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Organizing Committee| 2013
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Keynote 3 — Extreme scale challenges: Can reconfigurable computing come to the rescue?Gokhale, Maya et al. | 2013
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A robust and low resource FPGA-based stereoscopic vision algorithmIbarra-Delgado, S. / Calvino, M. Hernandez / Mata, N. Guil / Gomez-Luna, J. et al. | 2013
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Alternative implementations of a fractional order control algorithm on FPGAsMuresan, Cristina I. / Mois, George / Folea, Silviu / Ionescu, Clara et al. | 2013
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Countermeasures against EM analysis for a secured FPGA-based AES implementationMaistri, P. / Tiran, S. / Maurine, P. / Koren, I. / Leveugle, R. et al. | 2013
- 1
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Design of low area-overhead ring oscillator PUF with large challenge spaceSahoo, Durga Prasad / Mukhopadhyay, Debdeep / Chakraborty, Rajat Subhra et al. | 2013
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Energy-efficient Median filter on FPGASanny, Andrea / Prasanna, Viktor K. et al. | 2013
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FPGA-based reconfigurable unit for image filtering in frequency domainLedesma-Carrillo, Luis M. / Lopez-Ramirez, Misael / Martinez-Herrera, Ana L. et al. | 2013
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Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graphYu, Bai / Alawad, Mohammed / Riera, Michael / Lin, Mingjie et al. | 2013
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Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocationHeisswolf, Jan / Singh, Maximilian / Kupper, Martin / Konig, Ralf / Becker, Jurgen et al. | 2013
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Keynote 2 — Past, current, and future of faster, cheaper, betterGallagher, Tim et al. | 2013
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An efficient application-specific instruction-set processor for packet classificationAhmed, Omar / Areibi, Shawki et al. | 2013
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BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman alignerLam, Bryant C. / Pascoe, Carlo / Schaecher, Scott / Lam, Herman / George, Alan D. et al. | 2013
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Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGASkalicky, Sam / Lopez, Sonia / Lukowiak, Marcin et al. | 2013
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Dynamic and partial reconfiguration of Zynq 7000 under LinuxKadi, Muhammed Al / Rudolph, Patrick / Gohringer, Diana / Hubner, Michael et al. | 2013
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Dynamic simulation of direct torque control of induction motors with FPGA based acceleratorsKia, Hamed S. / Zare, Mohammad A. / Kavasseri, Rejesh G. / Ababei, Cristinel et al. | 2013
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High level synthesis: Where are we? A case study on matrix multiplicationSkalicky, Sam / Wood, Christopher / Lukowiak, Marcin / Ryan, Matthew et al. | 2013
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Improving FPGA placement with a self-organizing mapBostelmann, Timm / Sawitzki, Sergei et al. | 2013
- 1
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RALP: Reconvergence-aware layer partitioning for 3D FPGAsLiu, Qingyu / Ma, Yuchun / Wang, Yu / Luk, Wayne / Bian, Jinian et al. | 2013
- 1
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A framework for PC applications with portable and scalable FPGA acceleratorsWeinhardt, Markus / Krieger, Alexander / Kinder, Thomas et al. | 2013
- 1
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A hierarchical parallel evolvable hardware based on network on chipWang, Jun Rong / Wang, Dan / Lai, Jin Mei et al. | 2013
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A scalable evolvable hardware processing arrayGallego, Angel / Mora, Javier / Otero, Andres / de la Torre, Eduardo / Riesgo, Teresa et al. | 2013
- 1
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Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtimeAnwer, Jahanzeb / Meisner, Sebastian / Platzner, Marco et al. | 2013
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Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)Pangracious, Vinod / Mehrez, Habib / Beltaief, Nizar / Marrakchi, Zied / Farooq, Umer et al. | 2013
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Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximationRodriguez-Garcia, A. / Pizano-Escalante, L. / Parra-Michel, R. / Longoria-Gandara, O. / Cortez, J. et al. | 2013
- 1
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Numerically efficient and biophysically accurate neuroprocessing platformMoctezuma, Juan Carlos / McGeehan, Joseph P. / Nunez-Yanez, Jose Luis et al. | 2013
- 1
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PolyNOC — A polymorphic thread simulator for NoC communication based embedded systemsPonpandi, Swamy D. / Zhang, Zhang / Tyagi, Akhilesh et al. | 2013
- 1
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Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platformSingla, Garbi / Tobajas, Felix / de Armas, Valentin et al. | 2013
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An effective window based legalization algorithm for FPGA placementWang, Yu / Shin, Hyunchul et al. | 2013
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Design of asynchronous systems on FPGA using direct mapping and synchronous specificationOliveira, Duarte L. / Bompean, Diego / Faria, Lester A. / Oliveira, Joao Luis V. et al. | 2013
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Parallel and configurable turbo decoder implementation for 3GPP-LTEGonzalez-Perez, Luis F. / Yllescas-Calderon, Lennin C. / Parra-Michel, R. et al. | 2013
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A platform for secure IP integration in Xilinx Virtex FPGAsEbrahim, Ali / Benkrid, Khaled / Khalifat, Jalal / Hong, Chuan et al. | 2013
- 1
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The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networksBahrebar, Poona / Stroobandt, Dirk et al. | 2013
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Energy-efficient architecture for stride permutation on streaming dataChen, Ren / Prasanna, Viktor K. et al. | 2013
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PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAsAysu, Aydin / Schaumont, Patrick et al. | 2013
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Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGAWeber, Raymond J. / Hogan, Justin A. / LaMeres, Brock J. et al. | 2013
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Efficient multilevel interconnect topology for cluster-based mesh FPGA architectureAmouri, Emna / Blanchardon, Adrien / Chotin-Avot, Roselyne / Mehrez, Habib / Marrakchi, Zied et al. | 2013
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Leakage power reduction in FPGA DSP circuits through algorithmic noise toleranceMora-Sanchez, Edgar / Anderson, Jason H. et al. | 2013
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NoC-based hardware function libraries for running multiple DSP algorithmsGea-Garcia, B. I. / Vazquez-Avila, J. L. / Sandoval-Arechiga, R. / Pizano-Escalante, J. L. / Parra-Michel, R. et al. | 2013
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[Copyright notice]| 2013
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Design and implementation of a modular, low latency, fault-aware, FPGA-based network interfaceAmmendola, Roberto / Biagionil, Andrea / Frezza, Ottorino / Cicero, Francesca Lo / Lonardo, Alessandro / Paolucci, Pier Stanislao / Rossetti, Davide / Simula, Francesco / Tosoratto, Laura / Vicini, Piero et al. | 2013
- 1
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A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512Shoufan, Abdulhadi et al. | 2013
- 1
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Lightweight and compact solutions for secure reconfiguration of FPGAsAbdellatif, Karim M. / Chotin-Avot, R. / Mehrez, H. et al. | 2013
- 1
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Optimal mapping of multiple packet lookup schemes onto FPGAHaria, Swapnil / Prasanna, Viktor et al. | 2013
- 1
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Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA acceleratorDohi, Keisuke / Fukumoto, Kota / Shibata, Yuichiro / Oguri, Kiyoshi et al. | 2013
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Processor arrays generation for matrix algorithms used in embedded platformsPerez-Andrade, Roberto / Torres-Huitzil, Cesar / Cumplido, Rene / Campos, Juan M. et al. | 2013
- 1
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Real-timerange image preprocessing on FPGAsSchmid, Moritz / Blocherer, Markus / Hannig, Frank / Teich, Jurgen et al. | 2013
- 1
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A single-chip solution for the secure remote configuration of FPGAs using bitstream compressionVliegen, Jo / Mentcns, Nele / Verbauwhede, Ingrid et al. | 2013
- 1
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Timing error handling on CGRAsSchweizer, Thomas / Rosenstiel, Wolfgang / Ferreira, Luigi Vaz / Ritt, Marcus et al. | 2013
- 1
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A delay-based PUF design using multiplexer chainsHuang, Miaoqing / Li, Shiming et al. | 2013
- 1
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A restricted dynamically reconfigurable architecture for low power processorsHirao, Takeshi / Kim, Dahoo / Hida, Itaru / Asai, Tetsuya / Motomura, Masato et al. | 2013
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FPGA prototyping of large reconfigurable ADPLL network for distributed clock generationShan, Chuan / Zianbetov, Eldar / Yu, Weiqiang / Anceau, Francois / Billoint, Olivier / Galayko, Dimitri et al. | 2013
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FPGA2: An open source framework for FPGA-GPU PCIe communicationThoma, Yann / Dassatti, Alberto / Molla, Daniel et al. | 2013
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Optimization techniques for a high level synthesis implementation of the Sobel filterMonson, Josh / Wirthlin, Mike / Hutchings, Brad L et al. | 2013
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Additional reviewers| 2013
- 1
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Keynote 1 — Moore's law, programmable logic and reconfigurable systemsTrimberger, Steve et al. | 2013
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A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2m)Reymond, Guillaume / Murillo, Victor et al. | 2013
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A high performance architecture for computing burrows-wheeler transform on FPGAsCheema, Umer I. / Khokhar, Ashfaq A. et al. | 2013
- 1
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Accuracy, cost, and performance tradeoffs for floating-point accumulationNagar, Krishna K. / Bakos, Jason D. et al. | 2013
- 1
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Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoCRakossy, Zoltan Endre / Aponte, Axel Acosta / Chattopadhyay, Anupam et al. | 2013
- 1
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Improving calibration precision of signal-delay-based time measurement systems in FPGAsHinkfoth, Matthias / Joost, Ralf / Salomon, Ralf et al. | 2013
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A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reorderingOrlandic, Milica / Svarstad, Kjetil et al. | 2013
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MCMA: A modular processing elements array based low-power coarse-grained reconfigurable acceleratorChaintreuil, Remi / Uno, Rie / Amano, Hideharu et al. | 2013
- 1
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ModHDL: A modular and expandable language for developing synchronous hardwareMay, Fabian / Mayer-Lindenberg, Friedrich et al. | 2013
- 1
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Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication frameworkThomas, Kevin L. / Thompson, Michael S. et al. | 2013
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Tree-less Huffman coding algorithm for embedded systemsHernandez, Marco Antonio Soto / Alvarado-Nava, Oscar / Rodriguez-Martinez, Eduardo / Zaragoza Martinez, Francisco J. et al. | 2013
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Papers by sessions| 2013
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A reconfigurable architecture for searching optimal software code to implement block cipher permutation matricesKavun, Elif Bilge / Leander, Gregor / Yalcind, Tolga et al. | 2013
- 1
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Enhancing productivity with back-end similarity matching of digital circuits for IP reuseZeng, Kevin / Athanas, Peter et al. | 2013
- 1
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Loopy — An open-source TCP/IP rapid prototyping and validation frameworkde Schryver, Christian / Schlafer, Philipp / Wehn, Norbert / Fischer, Thomas / Poetzsch-Heffter, Arnd et al. | 2013
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Max-hashing fragments for large data sets detectionDavid, Jean Pierre et al. | 2013
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ReCompAc: Reconfigurable compute acceleratorDuric, Milovan / Palomar, Oscar / Smith, Aaron et al. | 2013
- 1
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SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function unitsDumitriu, Victor / Kirischian, Lev et al. | 2013
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Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysisNavas, Byron / Oberg, Johnny / Sander, Ingo et al. | 2013
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Message from chairs| 2013
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Technical demonstrations session| 2013
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A VLSI architecture for the QR decomposition based on the MCGR algorithmCervantes-Lozano, Pedro / Gonzalez-Perez, Luis F. / Garcia-Garcia, Andres D. et al. | 2013
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Extracting memory-level parallelism through reconfigurable hardware tracesLin, Mingjie / Cheng, Shaoyi / Wawrzynek, John et al. | 2013
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Exploring the problems of placement and mapping in NoC-based reconfizurable systemsFilho, Jonas Gomes / Chau, Wang Jiang et al. | 2013
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Online heavy hitter detector on FPGATong, Da / Prasanna, Viktor et al. | 2013
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Range tree-linked list hierarchical search structure for packet classification on FPGAsErdem, Oguzhan / Carus, Aydin et al. | 2013
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[Front cover]| 2013