Rapid embedded hardware/software system generation (English)
- New search for: Peddersen, J.
- New search for: Seng Lin Shee,
- New search for: Janapsatya, A.
- New search for: Parameswaran, S.
- New search for: Peddersen, J.
- New search for: Seng Lin Shee,
- New search for: Janapsatya, A.
- New search for: Parameswaran, S.
In:
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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111-116
;
2005
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ISBN:
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ISSN:
- Conference paper / Electronic Resource
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Title:Rapid embedded hardware/software system generation
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Contributors:Peddersen, J. ( author ) / Seng Lin Shee, ( author ) / Janapsatya, A. ( author ) / Parameswaran, S. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2005-01-01
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Size:177259 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
-
Tutorial: Power-aware, reliable microprocessor designBose, P. et al. | 2005
- 7
-
High-speed interconnect technology: on-chip and off-chipSapatnekar, S. / Roychowdhury, J. / Harjani, R. et al. | 2005
- 8
-
Testing nanometer digital integrated circuits: myths, reality and the road aheadBlanton, S. / Mitra, S. et al. | 2005
- 10
-
SoC design methodology: a practical approachJain, A. / Saha, A. / Rao, J. et al. | 2005
- 12
-
Test methodologies in the deep submicron era - analog, mixed-signal and RFChatterjee, A. / Keshavarzi, A. / Patra, A. / Mukhopadhyay, S. et al. | 2005
- 14
-
Recent advances in verification, equivalence checking & SAT-solversPradhan, D. / Abadir, M. / Varea, M. et al. | 2005
- 15
-
Compact MOSFET models for low power analog CMOS designBhattacharrya, A.B. et al. | 2005
- 16
-
Physics and technology: towards low-power DSM designMukhopadhyay, D. / Basu, P.K. / Rao, V.R. et al. | 2005
- 18
-
Architectural, system level and protocol level techniques for power optimization for networked embedded systemsBenini, L. / Shuklam SK, / Gupta, R.K. et al. | 2005
- 21
-
The high walls have crumpled [system-on-a-chip technology]Liu, C.L. et al. | 2005
- 25
-
65nm ombudsmanVucurevich, T. et al. | 2005
- 26
-
ESL - the next leadership opportunity for India?Naumann, A. et al. | 2005
- 27
-
VLSI design challenges for gigascale integrationBorkar, S. et al. | 2005
- 31
-
Moore's law is unconstitutionalRhines, W.C. et al. | 2005
- 35
-
Configurable processor the building block for SOC (system-on-a-chip)Fu, B. et al. | 2005
- 36
-
Modeling usable & reusable transactors in system VerilogBergeron, J. et al. | 2005
- 37
-
Optimizing SoC manufacturabilityZorian, Y. et al. | 2005
- 41
-
Tuple detection for path delay faults: a method for improving test set qualityPomeranz, I. / Reddy, S.M. et al. | 2005
- 47
-
A delay test to differentiate resistive interconnect faults from weak transistor defectsHaihua Yan, / Singh, A.D. et al. | 2005
- 53
-
Efficient space/time compression to reduce test data volume and testing time for IP coresLei Li, / Chakrabarty, K. / Kajihara, S. / Swaminathan, S. et al. | 2005
- 59
-
On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratiosHuaxing Tang, / Chen Wang, / Rajski, J. / Reddy, S.M. / Tyszer, J. / Pomeranz, I. et al. | 2005
- 65
-
Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chipLingappan, L. / Ravi, S. / Raghunathan, A. / Jha, N.K. / Chakradhar, S.T. et al. | 2005
- 71
-
Cellular automata based test structures with logic foldingSikdar, B.K. / Das, S. / Roy, S. / Ganguly, N. / Das, D.K. et al. | 2005
- 77
-
Electromigration-aware physical design of integrated circuitsLienig, J. / Jerke, G. et al. | 2005
- 85
-
Variance reduction in Monte Carlo capacitance extractionBatterywala, S.H. / Desai, M.P. et al. | 2005
- 91
-
A fast buffered routing tree construction algorithm under accurate delay modelYibo Wang, / Yici Cai, / Xianlong Hong, et al. | 2005
- 97
-
Improved layout-driven area-constrained timing optimization by net bufferingMurgai, R. et al. | 2005
- 105
-
Battery model for embedded systemsRao, V. / Singhal, G. / Kumar, A. / Navet, N. et al. | 2005
- 111
-
Rapid embedded hardware/software system generationPeddersen, J. / Seng Lin Shee, / Janapsatya, A. / Parameswaran, S. et al. | 2005
- 117
-
A unified architecture for adaptive compression of data and code on embedded systemsLekatsas, H. / Henkel, J. / Venkata Jakkula, / Srimat Chakradhar, et al. | 2005
- 124
-
A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systemsBhojwani, P. / Mahapatra, R. / Eun Jung Kim, / Chen, T. et al. | 2005
- 130
-
A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCsAshok Narasimhan, / Shantanu Divekar, / Praveen Elakkumanan, / Ramalingam Sridhar, et al. | 2005
- 134
-
Implementing LDPC decoding on network-on-chipTheocharides, T. / Link, G. / Vijaykrishnan, N. / Irwin, M.J. et al. | 2005
- 138
-
A RISC hardware platform for low power JavaCapewell, P. / Watson, I. et al. | 2005
- 147
-
A low power reprogrammable parallel processing VLSI architecture for computation of B-spline based medical image processing system for fast characterization of tiny objects suspended in cellular fluidSabyasachi Mondal, / Arijit De, / Biswas, P.K. et al. | 2005
- 153
-
Design of a low power image watermarking encoder using dual voltage and frequencyMohanty, S.P. / Ranganathan, N. / Balakrishnan, K. et al. | 2005
- 159
-
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltagesDiril, A.U. / Dhillon, Y.S. / Abhijit Chatterjee, / Singh, A.D. et al. | 2005
- 165
-
Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuitsShengqi Yang, / Wolf, W. / Vijaykrishnan, N. / Yuan Xie, / Wenping Wang, et al. | 2005
- 171
-
Charge-recovery power clock generators for adiabatic logic circuitsArsalan, M. / Shams, M. et al. | 2005
- 175
-
Power optimization in current mode circuitsBhat, M.S. / Jamadagni, H.S. et al. | 2005
- 183
-
Lazy constraints and SAT heuristics for proof-based abstractionAarti Gupta, / Malay Ganai, / Pranav Ashar, et al. | 2005
- 189
-
Q-PREZ: QBF evaluation using partition, resolution and elimination with ZBDDsChandrasekar, K. / Hsiao, M.S. et al. | 2005
- 195
-
A verification system for transient response of analog circuits using model checkingTathagato Rai Dastidar, / Chakrabarti, P.P. et al. | 2005
- 201
-
Formal methods for analyzing the completeness of an assertion suite against a high-level fault modelSayanlan Das, / Ansuman Banerjee, / Prasenjit Basu, / Pallab Dasgupta, / Chakrabarti, P.P. / Chunduri Rama Mohan, / Fix, L. et al. | 2005
- 207
-
A universal random test generator for functional verification of microprocessors and system-on-chipUday Bhaskar, K. / Prasanth, M. / Chandramouli, G. / Kamakoti, V. et al. | 2005
- 213
-
Syntactic transformation of assume-guarantee assertions: from sub-modules to modulesBasu, P. / Dasgupta, P. / Chakrabarti, P.P. et al. | 2005
- 221
-
Design, testing, and applications of digital microfluidics-based biochipsChakrabarty, K. et al. | 2005
- 229
-
Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologiesRui Zhang, / Gupta, P. / Jha, N.K. et al. | 2005
- 235
-
Design, fabrication, testing and simulation of porous silicon based smart MEMS pressure sensorPramanik, C. / Islam, T. / Saha, H. / Bhattacharya, J. / Banerjee, S. / Dey, S. et al. | 2005
- 241
-
A nanosensor array-based VLSI gas discriminatorIrick, K.M. / Xu, W. / Vijaykrishnan, N. / Irwin, M.J. et al. | 2005
- 249
-
Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arraysChakraborty, A. et al. | 2005
- 255
-
Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adderBabu, H.M.H. / Chowdhury, A.R. et al. | 2005
- 261
-
Optimization of mixed logic circuits with application to a 64-bit static adderYuanzhong Wan, / Shams, M. et al. | 2005
- 267
-
Behavioral synthesis of data-dominated circuits for minimal energy implementationXiaoyong Tang, / Tianyi Jiang, / Jones, A. / Banerjee, P. et al. | 2005
- 274
-
Integrated on-chip storage evaluation in ASIP synthesisManoj Kumar Jain, / Balakrishnan, M. / Anshul Kumar, et al. | 2005
- 280
-
Extracting exact finite state machines from behavioral SystemC descriptionsVikram Singh Saun, / Preeti Ranjan Panda, et al. | 2005
- 289
-
A system-level alternate test approach for specification test of RF transceivers in loopback modeHaider, A. / Bhattacharya, S. / Srinivasan, G. / Chatterjee, A. et al. | 2005
- 295
-
Effects of technology and dimensional scaling on input loss prediction of RF MOSFETsDas, T. / Washburn, C. / Mukund, P.R. / Howard, S. / Paradis, K. / Jung-Geau Jang, / Kolnik, J. / Burleson, J. et al. | 2005
- 301
-
Design of multi-GHz asynchronous pipelined circuits in MOS current-mode logicTin Wai Kwan, / Shams, M. et al. | 2005
- 307
-
Design of second-order sub-bandgap mixed-mode voltage reference circuit for low voltage applicationsPaul, R. / Patra, A. / Baranwal, S. / Dash, K. et al. | 2005
- 313
-
A 160 MSPS 8-bit pipeline based ADCHaider, S. / Ghosh, A. / Ravi sankar Prasad, / Anirban Chatierjeee, / Swapna Banerjee, et al. | 2005
- 319
-
A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm/sup 2/ segmented current steering CMOS DACHaider, S. / Banerjee, S. / Ghosh, A. / Ravi sankar Prasad, / Chatterjee, A. / Kumar Dey, S. et al. | 2005
- 319
-
A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 segmented current steering CMOS DACHaider, S. / Banerjee, S. / Ghosh, A. / Ravi sankar Prasad / Chatterjee, A. / Kumar Dey, S. et al. | 2005
- 325
-
Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communicationKatoch, A. / Meijer, M. / Jain, S.K. et al. | 2005
- 330
-
An efficient methodology for noise characterizationVarshney, G.K. / Chandrasekar, S. et al. | 2005
- 336
-
Application of DC transfer characteristics in the elimination of redundant vectors for transient noise characterization of static CMOS circuitsChandrasekar, S. / Visvanathan, V. / Kumar Varshney, G. et al. | 2005
- 342
-
Crosstalk noise analysis at multiple frequenciesShrivastava, S. / Chandrasekar, S. et al. | 2005
- 348
-
Worst-case crosstalk noise analysis based on dual-exponential noise metricsJiaxing Sun, / Yun Zheng, / Qing Ye, / Tianchun Ye, et al. | 2005
- 354
-
ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chipsPalit, A.K. / Meyer, V. / Anheier, W. / Schloeffel, J. et al. | 2005
- 362
-
Impact of process variations on multi-level signaling for on-chip interconnectsVenkatraman, V. / Burleson, W. et al. | 2005
- 368
-
A quasi-delay-insensitive method to overcome transistor variationBrej, C. / Garside, J.D. et al. | 2005
- 374
-
Influence of leakage reduction techniques on delay/leakage uncertaintyYuh-Fang Tsai, / Vijaykrishnan, N. / Yuan Xie, / Irwin, M.J. et al. | 2005
- 380
-
Multivariate normal distribution based statistical timing analysis using global projection and local expansionBaohua Wang, / Mazumder, P. et al. | 2005
- 386
-
Evaluation of device parameters of HfO2/SiO2/Si gate dielectric stack for MOSFETsMadan, A. / Bose, S.C. / George, P.J. / Chandra Shekhar et al. | 2005
- 386
-
Evaluation of device parameters of HfO/sub 2//SiO/sub 2//Si gate dielectric stack for MOSFETsMadan, A. / Bose, S.C. / George, P.J. / Chandra Shekhar, et al. | 2005
- 392
-
Impact of channel engineering on unity gain frequency and noise-figure in 90nm NMOS transistor for RF applicationsSrinivasan, R. / Navakanta Bhat, et al. | 2005
- 399
-
A methodology and tooling enabling application specific processor designHoffmann, A. / Fiedler, F. / Nohl, A. / Parupalli, S. et al. | 2005
- 405
-
An efficient end to end design of Rijndael cryptosystem in 0.18 mu CMOSMukhopadhyay, D. / RoyChowdhury, D. et al. | 2005
- 405
-
An efficient end to end design of Rijndael cryptosystem in 0.18 /spl mu/ CMOSMukhopadhyay, D. / RoyChowdhury, D. et al. | 2005
- 411
-
ADOPT: an approach to activity based delay optimizationArora, G. / Sharma, A. / Nagchoudhury, D. / Balaknshnan, M. et al. | 2005
- 417
-
Coding for reliable on-chip buses: fundamental limits and practical codesSridhara, S.R. / Shanbhag, N.R. et al. | 2005
- 423
-
False path and clock scheduling based yield-aware gate sizingJeng-Liang Tsai, / Dong Hyun Baik, / Chung-Ping Chen, C. / Saluja, K.K. et al. | 2005
- 427
-
Variable resizing for area improvement in behavioral synthesisGopalakrishnan, R. / Moona, R. et al. | 2005
- 433
-
Orthogonal circuit visualization improved by merging the placement and routing phasesEschbach, T. / Gunther, W. / Becker, B. et al. | 2005
- 439
-
Lithography driven layout designGarg, M. / Le Cam, L. / Gonzalez, M. et al. | 2005
- 445
-
Non-Manhattan routing using a Manhattan routerHursey, E. / Jayakumar, N. / Khatri, S.P. et al. | 2005
- 451
-
Placement and routing for 3D-FPGAs using reinforcement learning and support vector machinesManimegalai, R. / Siva Soumya, E. / Muralidharan, V. / Ravindran, B. / Kamakoti, V. / Bhatia, D. et al. | 2005
- 457
-
Automatic device layout generation for analog layout retargetingHartono, R. / Jangkrajarng, N. / Bhattacharya, S. / Richard Shi, C.J. et al. | 2005
- 463
-
Floorplan-based crosstalk estimation for macrocell-based designsGupta, S. / Katkoori, S. / Sankaran, S. et al. | 2005
- 471
-
Distance restricted scan chain reordering to enhance delay fault coverageWei Li, / Seongmoon Wang, / Chakradhar, S.T. / Reddy, S.M. et al. | 2005
- 479
-
A novel algorithm for testing crosstalk induced delay faults in VLSI circuitsAniket, / Arunachalam, R. et al. | 2005
- 485
-
An ultra-fast, on-chip BiST for RF low noise amplifiersGopalan, A. / Das, T. / Washburn, C. / Mukund, P.R. et al. | 2005
- 491
-
On finding consecutive test vectors in a random sequence for energy-aware BIST designZhane, S. / Seth, S.C. / Bhattacharya, B.B. et al. | 2005
- 497
-
A framework for distributed and hierarchical design-for-testRavikumar, C.P. / Dandamudi, R. / Devanathan, V.R. / Haldar, N. / Kiran, K. / Kumar, V. et al. | 2005
- 504
-
A novel specification based test pattern generation using genetic algorithm and waveletsKalpana, P. / Gunavathi, K. et al. | 2005
- 511
-
Programmable high frequency RC oscillatorBala, F. / Nandy, T. et al. | 2005
- 516
-
Exact analytical equations for predicting nonlinear phase errors and jitter in ring oscillatorsRoychowdhury, J. et al. | 2005
- 522
-
On-chip voltage regulator with improved transient responseMaity, A. / Raghavendra, R.G. / Mandal, P. et al. | 2005
- 528
-
An active learning scheme using support vector machines for analog circuit feasibility classificationDing, M. / Vemur, R.I. et al. | 2005
- 535
-
A hierarchical cost tree mutation approach to optimization of analog circuitsSomani, A. / Chakrabarti, P.P. / Patra, A. et al. | 2005
- 539
-
A wide-swing V/sub T/-referenced circuit with insensitivity to device mismatchChih-Jen Yen, / Wen-Yaw Chung, / Mely Chen Chi, et al. | 2005
- 545
-
Dictionary based code compression for variable length instruction encodingsDas, D. / Kumar, R. / Chakrabarti, P.P. et al. | 2005
- 551
-
Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processorsFei Sun, / Jha, N.K. / Ravi, S. / Raghunathan, A. et al. | 2005
- 557
-
Evaluation of speed and area of clustered VLIW processorsTerechko, A. / Garg, M. / Corporaal, H. et al. | 2005
- 564
-
A technique for throughput and register optimization during resource constrained pipelined schedulingRangan, N. / Chatha, K.S. et al. | 2005
- 570
-
Dynamically exploiting frequent operand values for energy efficiency in integer functional unitsGandhi, K.R. / Mahapatra, N.R. et al. | 2005
- 579
-
Power monitors: a framework for system-level power estimation using heterogeneous power modelsBansal, N. / Lahiri, K. / Raghunathan, A. / Chakradhar, S.T. et al. | 2005
- 586
-
Estimation of switching activity in sequential circuits using dynamic Bayesian networksBhanja, S. / Lingasubramanian, K. / Ranganathan, N. et al. | 2005
- 592
-
Energy-efficient compressed address transmissionJiangjiang Liu, / Sundaresan, K. / Mahapatra, N.R. et al. | 2005
- 598
-
Variable input delay CMOS logic for low power designRaja, T. / Agrawal, V.D. / Bushnell, M.L. et al. | 2005
- 606
-
Gate leakage and its reduction in deep submicron SRAMGoel, A. / Mazhari, B. et al. | 2005
- 615
-
Revisiting VLSI interconnects in deep sub-micron: some open questionsDasgupta, P. et al. | 2005
- 623
-
ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesisSrinivasan, K. / Chatha, K.S. et al. | 2005
- 629
-
Projection based fast passive compact macromodeling of high-speed VLSI circuits and interconnectsSaraswat, D. / Achar, R. / Nakhla, M. et al. | 2005
- 634
-
A low-swing differential signalling scheme for on-chip global interconnectsNarasimhan, A. / Kasotiya, M. / Sridhar, R. et al. | 2005
- 640
-
Performances of coupled interconnect lines: the impact of inductance and routing orientationDeschacht, D. / Lopez, A. et al. | 2005
- 647
-
On physical-aware synthesis of vertically integrated 3D systemsMukherjee, M. / Vemuri, R. et al. | 2005
- 653
-
Energy efficient hardware synthesis of polynomial expressionsHosangadi, A. / Kastner, R. / Fallah, F. et al. | 2005
- 659
-
Algorithmic implementation of low-power high performance FIR filtering IP coresWang, C.H. / Erdogan, A.T. / Arslan, T. et al. | 2005
- 663
-
On-line synthesis for partially reconfigurable FPGAsRenqiu Huang, / Vemuri, R. et al. | 2005
- 669
-
A combinational logic mapper for Actel's SX/AX familyChattopadhyay, S. / Kumar Dewangan, M. et al. | 2005
- 673
-
A novel approach to minimizing reconfiguration cost for LUT-based FPGAsPrasad Raghuraman, K. / Haibo Wang, / Tragoudas, S. et al. | 2005
- 679
-
Power variability and its impact on designDevgan, A. / Nassif, S. et al. | 2005
- 685
-
An accurate energy and thermal model for global signal busesSundaresan, K. / Mahapatra, N.R. et al. | 2005
- 691
-
Hot spots and zones in a chip: a geometrician's viewMajumder, S. / Sur-Kolay, S. / Nandy, S.C. / Bhattacharya, B.B. / Chakraborty, B. et al. | 2005
- 697
-
Direct temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 /spl mu/m SOI technologiesJoshi, R.V. / Kang, S.S. / Zamclmar, N. / Mocuta, A. / Chuang, C.T. / Pascual-Gutierrez, J.A. et al. | 2005
- 705
-
DFM: linking design and manufacturingRaghvendra, S. / Hurat, P. et al. | 2005
- 709
-
The impact of inductance on transients affecting gate oxide reliabilityNagaraj, N.S. / Hunter, W.R. / Balsara, P. / Cantrell, C. et al. | 2005
- 717
-
An accurate probabilistic model for error detectionRejimon, T. / Bhanja, S. et al. | 2005
- 723
-
Using contrapositive law in an implication graphDave, K.K. / Agrawal, V.D. / Bushnell, M.L. et al. | 2005
- 730
-
Off-line testing of asynchronous circuitsKoppad, D. / Bystrov, A. / Yakovlev, A. et al. | 2005
- 736
-
Detecting SEU-caused routing errors in SRAM-based FPGAsReddy, E.S.S. / Chandrasekhar, V. / Sashikanth, M. / Kamakoti, V. / Vijaykrishnan, N. et al. | 2005
- 742
-
Multiple fault testing of logic resources of SRAM-based FPGAsGoyal, S. / Choudhuryt, M. / Rao, S.S.S.P. / Kalyan Kumar, L. et al. | 2005
- 751
-
A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systemsKhan, Z. / Arslan, T. / Erdogan, A.T. et al. | 2005
- 757
-
Application of Douglas-Peucker algorithm to generate compact but accurate IBIS modelsNandakumar, G.N. / Patel, N. / Reddy, R. / Kothandaraman, M. et al. | 2005
- 762
-
An effective VHDL-AMS simulation algorithm with eventGhasemi, H.R. / Navabi, Z. et al. | 2005
- 768
-
Application of alpha power law models to PLL design methodologySuresh, B. / Visvanathan, V. / Krishnan, R.S. / Jamadagni, H.S. et al. | 2005
- 774
-
Exploiting radio hierarchies for power-efficient wireless device discovery and connection setupPering, T. / Raghunathan, V. / Want, R. et al. | 2005
- 780
-
Fully integrated CMOS frequency synthesizer for ZigBee applicationsSingh, S.K. / Bhattacharyya, T.K. / Dutta, A. et al. | 2005
- 787
-
Computer aided test (CAT) tool for mixed signal SOCsBanerjee, S. / Mukhopadhyay, D. / Chowdhury, D.R. et al. | 2005
- 791
-
A novel low power 16/spl times/16 content addressable memory using PALBala, G.J. / Perinbam, J.R.P. et al. | 2005
- 791
-
A novel low power 16x16 content addressable memory using PALBala, G.J. / Perinbam, J.R.P. et al. | 2005
- 795
-
A principal component neural network-based face recognition system and ASIC implementationChakka Siva Sai Prasanna, / Sudha, N. / Kamakoti, V. et al. | 2005
- 799
-
Synthesis of asynchronous circuits using early data validityGupta, N. / Edwards, D.A. et al. | 2005
- 804
-
A low overhead high speed histogram based test methodology for analog circuits and IP coresBahukudumbi, S. / Bharath, K. et al. | 2005
- 808
-
A methodology for fast vector based power supply and substrate noise analysesDebnath, S.P. / Sukumar, J. / Udaykumar, H. et al. | 2005
- 812
-
An operational amplifier model for test planning at behavioral levelRomero, E. / Peretti, G. / Marques, C. et al. | 2005
- 816
-
Memory-centric motion estimatorBeric, A. / Sethuraman, R. / van Meerbergen, J. / de Haan, G. et al. | 2005
- 820
-
SCINDY: logic crosstalk delay fault simulation in sequential circuitsPhadoongsidhi, M. / Saluja, K.K. et al. | 2005
- 824
-
A new asymmetric skewed buffer design for runtime leakage power reductionYu-Shiang Lin, / Sylvester, D. et al. | 2005
- 828
-
A relative comparative based datapath for increasing resolution in a capacitive fingerprint sensor chipOjha, M.M. / Anand, A.K. / Visweswaran, G.S. / Nagchoudhuri, D. et al. | 2005
- 832
-
Applicability of general purpose processors to network applicationsDurbhakula, M. et al. | 2005
- 836
-
Power switch network design for MTCMOSVilangudipitchai, R. / Balsara, P.T. et al. | 2005
- 842
-
Structural fault diagnosis in charge-pump based phase-locked loopsMedury, A. / Carlson, I. / Alvandpour, A. / Stensby, J. et al. | 2005
- 846
-
Dual-edge triggered static pulsed flip-flopsAliakbar Ghadiri, / Hamid Mahmoodi, et al. | 2005
- 850
-
A new CMOS current conveyors based translinear loop for log-domain circuit designDutta, D. / Serdijn, W.A. / Swapna Banerjee, / Sriram Gupta, et al. | 2005
- 854
-
A high accuracy bandgap reference with chopped modulator to compensate MOSFET mismatchLiu Lian-xi, / Yang Yin-tang, / Zhu Zhang-ming, et al. | 2005
- 858
-
A high-efficiency, dual-mode, dynamic, buck-boost power supply IC for portable applicationsSahu, B. / Rincon-Mora, G.A. et al. | 2005
- 862
-
Design issues in switched capacitor ladder filtersBasu, A. / Dhar, A.S. et al. | 2005
- 866
-
ASIC design of the linearisation circuit of a PTC thermistorChowdhury, S.R. / Pramanik, C. / Saha, H. et al. | 2005
- 870
-
A reconfigurable oscillator topology for dual-band operationTien-Ling Hsieh, / Ranjit Gharpurey, et al. | 2005
- 874
-
Reducing leakage with mixed-V/sub th/ (MVT)Sill, F. / Grassert, F. / Timmermann, D. et al. | 2005
- 874
-
Reducing leakage with mixed-Vth (MVT)Sill, F. / Grassert, F. / Timmermann, D. et al. | 2005
- 878
-
System in a package design of a RF front end system using application specific reduced order modelsNayak, G. / Washburn, C. / Mukund, P.R. et al. | 2005
- 883
-
Author index| 2005
- c1
-
Proceedings. 18th International Conference on VLSI Design| 2005
- i
-
18th International Conference on VLSI Design - Title Page| 2005
- iv
-
18th International Conference on VLSI Design - Copyright Page| 2005
- v
-
18th International Conference on VLSI Design - Table of Contents| 2005
- xviii
-
Message from the General Chairs| 2005
- xxi
-
Message from the Program Chairs| 2005
- xxiii
-
Conference Committee| 2005
- xxix
-
list-reviewer| 2005
- xxv
-
Steering Committee| 2005
- xxvi
-
Technical Program Committee| 2005
- xxviii
-
VLSI Design 2004 Conference Awards| 2005
- xxxii
-
VLSI Design Conference History| 2005
- xxxiii
-
Embedded Systems Design Conference History| 2005