Ternary Propagation-Based Local Search for more Bit-Precise Reasoning (English)
- New search for: Niemetz, Aina
- New search for: Preiner, Mathias
- New search for: Niemetz, Aina
- New search for: Preiner, Mathias
In:
2020 Formal Methods in Computer Aided Design (FMCAD)
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214-224
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2020
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ISBN:
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- Conference paper / Electronic Resource
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Title:Ternary Propagation-Based Local Search for more Bit-Precise Reasoning
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Contributors:Niemetz, Aina ( author ) / Preiner, Mathias ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2020-09-21
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Size:2479964 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design FMCAD 2020| 2020
- 1
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Back| 2020
- 1
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A Theoretical Framework for Symbolic Quick Error DetectionLonsing, Florian / Mitra, Subhasish / Barrett, Clark et al. | 2020
- 1
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Anytime Algorithms for MaxSAT and BeyondNadel, Alexander et al. | 2020
- 1
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Copyright| 2020
- 1
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Preface| 2020
- 1
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Tutorial on World-Level Model CheckingBiere, Armin et al. | 2020
- 1
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Table of Contents| 2020
- 1
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From Correctness to High QualityKupferman, Orna et al. | 2020
- 1
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Organizing Committee| 2020
- 1
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How testable is business software?Schrammel, Peter et al. | 2020
- 1
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The FMCAD 2020 Student ForumSchrammel, Peter et al. | 2020
- 1
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Message from the Steering Committee Chairman| 2020
- 1
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Formal Verification for Natural and Engineered Biological SystemsKugler, Hillel et al. | 2020
- 7
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Effective System Level Liveness VerificationFedotov, Alexander / Keiren, Jeroen J.A. / Schmaltz, Julien et al. | 2020
- 16
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Accelerating Parallel Verification via Complementary Property Partitioning and Strategy ExplorationDureja, Rohit / Baumgartner, Jason / Kanzelman, Robert / Williams, Mark / Rozier, Kristin Y. et al. | 2020
- 36
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Runtime Verification on FPGAs with LTLf SpecificationsTracy, Tommy / Tabajara, Lucas M. / Vardi, Moshe / Skadron, Kevin et al. | 2020
- 47
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Distributed Bounded Model CheckingChatterjee, Prantik / Roy, Subhajit / Diep, Bui Phi / Lal, Akash et al. | 2020
- 57
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EUFicient Reachability in Software with ArraysBueno, Denis / Cox, Arlen / Sakallah, Karem et al. | 2020
- 67
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Thread-modular Counter Abstraction for Parameterized Program SafetyPani, Thomas / Weissenbacher, Georg / Zuleger, Florian et al. | 2020
- 77
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Incremental Verification by SMT-based Summary RepairAsadi, Sepideh / Blicha, Martin / Hyvarinen, Antti / Fedyukovich, Grigory / Sharygina, Natasha et al. | 2020
- 83
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Reactive Synthesis from Extended Bounded Response LTL SpecificationsCimatti, Alessandro / Geatti, Luca / Gigante, Nicola / Montanari, Angelo / Tonetta, Stefano et al. | 2020
- 93
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SYSLITE: Syntax-Guided Synthesis of PLTL Formulas from Finite TracesArif, M. Fareed / Larraz, Daniel / Echeverria, Mitziu / Reynolds, Andrew / Chowdhury, Omar / Tinelli, Cesare et al. | 2020
- 104
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Learning Properties in LTL ∩ ACTL from Positive Examples OnlyEhlers, Rudiger / Gavran, Ivan / Neider, Daniel et al. | 2020
- 113
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Automating Compositional Analysis of Authentication ProtocolsZhang, Zichao / de Amorim, Arthur Azevedo / Jia, Limin / Pasareanu, Corina S. et al. | 2020
- 119
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Selecting Stable Safe Configurations for Systems Modelled by Neural Networks with ReLU ActivationBrauBe, Franz / Khasidashvili, Zurab / Korovin, Konstantin et al. | 2020
- 128
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Parallelization Techniques for Verifying Neural NetworksWu, Haoze / Ozdemir, Alex / Zeljic, Aleksandar / Julian, Kyle / Irfan, Ahmed / Gopinath, Divya / Fouladi, Sadjad / Katz, Guy / Pasareanu, Corina / Barrett, Clark et al. | 2020
- 138
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Formal Methods with a Touch of MagicAlamdari, Par Alizadeh / Avni, Guy / Henzinger, Thomas A. / Lukina, Anna et al. | 2020
- 148
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Art: Abstraction Refinement-Guided Training for Provably Correct Neural NetworksLin, Xuankang / Zhu, He / Samanta, Roopsha / Jagannathan, Suresh et al. | 2020
- 158
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Automating Modular Verification of Secure Information FlowPick, Lauren / Fedyukovich, Grigory / Gupta, Aarti et al. | 2020
- 169
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Angelic Checking within Static Driver Verifier: Towards high-precision defects without (modeling) costLahiri, Shuvendu K. / Lal, Akash / Gopinath, Sridhar / Nutz, Alexander / Levin, Vladimir / Kumar, Rahul / Deisinger, Nate / Lichtenberg, Jakob / Bansal, Chetan et al. | 2020
- 179
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Model Checking Software-Defined Networks with Flow Entries that Time OutKlimis, Vasileios / Parisis, George / Reus, Bernhard et al. | 2020
- 185
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Using model checking tools to triage the severity of security bugs in the Xen hypervisorCook, Byron / Dobel, Bjorn / Kroening, Daniel / Manthey, Norbert / Pohlack, Martin / Polgreen, Elizabeth / Tautschnig, Michael / Wieczorkiewicz, Pawel et al. | 2020
- 194
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Verifying Properties of Bit-vector Multiplication Using Cutting Planes ReasoningLiew, Vincent / Beame, Paul / Devriendt, Jo / Elffers, Jan / Nordstrom, Jakob et al. | 2020
- 205
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On Optimizing a Generic Function in SATNadel, Alexander et al. | 2020
- 214
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Ternary Propagation-Based Local Search for more Bit-Precise ReasoningNiemetz, Aina / Preiner, Mathias et al. | 2020
- 225
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Reductions for Strings and Regular Expressions RevisitedReynolds, Andrew / Notzlit, Andres / Barrett, Clark / Tinelli, Cesare et al. | 2020
- 236
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Switss: Computing Small Witnessing SubsystemsJantsch, Simon / Harder, Hans / Funke, Florian / Baier, Christel et al. | 2020
- 245
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Smart Induction for Isabelle/HOL (Tool Paper)Nagashima, Yutaka et al. | 2020
- 255
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Trace Logic for Inductive Loop ReasoningGeorgiou, Pamina / Gleiss, Bernhard / Kovacs, Laura et al. | 2020
- 264
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The Proof Checkers Pacheck and Pastèque for the Practical Algebraic CalculusKaufmann, Daniela / Fleury, Mathias / Biere, Armin et al. | 2020
- IX
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Program Committee| 2020
- X
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Additional Reviewers| 2020