Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes (English)
- New search for: Tavares, Marcos B.S.
- New search for: Kunze, Steffen
- New search for: Matus, Emil
- New search for: Fettweis, Gerhard P.
- New search for: Tavares, Marcos B.S.
- New search for: Kunze, Steffen
- New search for: Matus, Emil
- New search for: Fettweis, Gerhard P.
In:
2008 International Conference on Application-Specific Systems, Architectures and Processors
;
215-220
;
2008
-
ISSN:
- Conference paper / Electronic Resource
-
Title:Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes
-
Contributors:Tavares, Marcos B.S. ( author ) / Kunze, Steffen ( author ) / Matus, Emil ( author ) / Fettweis, Gerhard P. ( author )
-
Published in:
-
Publisher:
- New search for: IEEE
-
Publication date:2008-07-01
-
Size:421247 byte
-
ISBN:
-
ISSN:
-
DOI:
-
Type of media:Conference paper
-
Type of material:Electronic Resource
-
Language:English
-
Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
-
Fast custom instruction identification by convex subgraph enumerationAtasu, Kubilay / Mencer, Oskar / Luk, Wayne / Ozturan, Can / Dundar, Gunhan et al. | 2008
- 7
-
Bit matrix multiplication in commodity processorsHilewitz, Yedidya / Lauradoux, Cedric / Lee, Ruby B. et al. | 2008
- 13
-
Synthesis of application accelerators on Runtime Reconfigurable HardwareAlle, Mythri / Varadarajan, Keshavan / Ramesh, Reddy C. / Nimmy, Joseph / Fell, Alexander / Rao, Adarsha / Nandy, S.K. / Narayan, Ranjani et al. | 2008
- 19
-
Floating point multiplication rounding schemes for interval arithmeticAmaricai, Alexandru / Vladutiu, Mircea / Udrescu, Mihai / Prodan, Lucian / Boncalo, Oana et al. | 2008
- 25
-
Fast multivariate signature generation in hardware: The case of rainbowBalasubramanian, Sundar / Carter, Harold W. / Bogdanov, Andrey / Rupp, Andy / Jintai Ding, et al. | 2008
- 31
-
Fault-tolerant dynamically reconfigurable NoC-based SoCHosseinabady, Mohammad / Nunez-Yanez, Jose et al. | 2008
- 37
-
Security processor with quantum key distributionLorunser, Thomas / Querasser, Edwin / Matyus, Thomas / Peev, Momtchil / Wolkerstorfer, Johannes / Hutter, Michael / Szekely, Alexander / Wimberger, Ilse / Pfaffel-Janser, Christian / Neppach, Andreas et al. | 2008
- 43
-
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transformMeher, P. K. / Patra, J. C. et al. | 2008
- 49
-
Reconfigurable Viterbi decoder on mesh connected multiprocessor architectureRajore, Ritesh / Garga, Ganesh / Jamadagni, H.S. / Nandy, S.K. et al. | 2008
- 55
-
Run-time thread sorting to expose data-level parallelismRamdas, Tirath / Egan, Gregory K. / Abramson, David / Baldridge, Kim K. et al. | 2008
- 61
-
A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systemsJovanovic, Slavisa / Tanougast, Camel / Weber, Serge et al. | 2008
- 67
-
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platformsDickin, David / Shannon, Lesley et al. | 2008
- 73
-
PERMAP: A performance-aware mapping for application-specific SoCsKiasari, A. E. / Hessabi, S. / Sarbazi-Azad, H. et al. | 2008
- 79
-
Low-cost implementations of NTRU for pervasive securityAtici, Ali Can / Batina, Lejla / Junfeng Fan, / Verbauwhede, Ingrid / Berna Ors Yalcin, S. et al. | 2008
- 85
-
On the high-throughput implementation of RIPEMD-160 hash algorithmKnezzevic, M. / Sakiyama, K. / Lee, Y. K. / Verbauwhede, I. et al. | 2008
- 91
-
Zodiac: System architecture implementation for a high-performance Network Security ProcessorWang Haixin, / Bai Guoqiang, / Chen Hongyi, et al. | 2008
- 97
-
Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transformsMeher, Pramod Kumar et al. | 2008
- 102
-
Resource efficient generators for the floating-point uniform and exponential distributionsThomas, David B. / Luk, Wayne et al. | 2008
- 108
-
Low discrepancy sequences for Monte Carlo simulations on reconfigurable platformsDalal, Ishaan L. / Stefan, Deian / Harwayne-Gidansky, Jared et al. | 2008
- 114
-
A subsampling pulsed UWB demodulator based on a flexible complex SVDVanderperren, Yves / Dehaene, Wim et al. | 2008
- 120
-
Dynamically reconfigurable regular expression matching architectureDivyasree, J. / Rajashekar, H. / Varghese, Kuruvilla et al. | 2008
- 126
-
An MPSoC architecture for the Multiple Target Tracking application in driver assistant systemKhan, Jehangir / Niar, Smail / Menhaj, Atika / Elhillali, Yassin / Dekeyser, Jean Luc et al. | 2008
- 132
-
Managing multi-core soft-error reliability through utility-driven cross domain optimizationWangyuan Zhang, / Tao Li, et al. | 2008
- 138
-
An efficient implementation of a phase unwrapping kernel on reconfigurable hardwareBraganza, Sherman / Leeser, Miriam et al. | 2008
- 144
-
A parallel hardware architecture for connected component labeling based on fast label mergingFlatt, Holger / Blume, Steffen / Hesselbarth, Sebastian / Schunemann, Torsten / Pirsch, Peter et al. | 2008
- 150
-
Operation shuffling over cycle boundaries for low energy L0 clusteringYuki Kobayashi, / Jayapala, Murali / Raghavan, Praveen / Catthoor, Francky / Masaharu Imai, et al. | 2008
- 156
-
An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processorKundeti, Vamsi / Yunsi Fei, / Rajasekaran, Sanguthevar et al. | 2008
- 162
-
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transformMohanty, Basant K. / Meher, Pramod K. et al. | 2008
- 167
-
Design space exploration of a cooperative MIMO receiver for reconfigurable architecturesMirzaei, Shahnam / Irturk, Ali / Kastner, Ryan / Weals, Brad T. / Cagley, Richard E. et al. | 2008
- 173
-
Dynamic holographic reconfiguration on a four-context ODRGAMao Nakajima, / Minoru Watanabe, et al. | 2008
- 179
-
FPGA-based hardware accelerator of the heat equation with applications on infrared thermographyPardo, F. / Lopez, P. / Cabello, D. et al. | 2008
- 185
-
FPGA based singular value decomposition for image processing applicationsRahmati, Masih / Sadri, Mohammad Sadegh / Naeini, Mehdi Ataei et al. | 2008
- 191
-
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAsJacob, Arpith / Buhler, Jeremy / Chamberlain, Roger D. et al. | 2008
- 197
-
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral OperatorLee, Jason / Shannon, Lesley / Yedlin, Matthew J. / Margrave, Gary F. et al. | 2008
- 203
-
Reconfigurable acceleration of microphone array algorithms for speech enhancementYiu, Ka Fai Cedric / Chun Hok Ho, / Grbric, Nedelko / Yao Lu, / Xiaoxiang Shi, / Luk, Wayne et al. | 2008
- 209
-
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standardsYang Sun, / Yuming Zhu, / Goel, Manish / Cavallaro, Joseph R. et al. | 2008
- 215
-
Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codesTavares, Marcos B.S. / Kunze, Steffen / Matus, Emil / Fettweis, Gerhard P. et al. | 2008
- 221
-
Buffer allocation for advanced packet segmentation in Network ProcessorsLlorente, Daniel / Karras, Kimon / Wild, Thomas / Herkersdorf, Andreas et al. | 2008
- 227
-
New insights on Ling addersVazquez, Alvaro / Antelo, Elisardo et al. | 2008
- 233
-
An efficient method for evaluating polynomial and rational function approximationsBrisebarre, Nicolas / Chevillard, Sylvain / Ercegovac, Milos D. / Muller, Jean-Michel / Torres, Serge et al. | 2008
- 239
-
Integer and floating-point constant multipliers for FPGAsBrisebarre, Nicolas / de Dinechin, Florent / Muller, Jean-Michel et al. | 2008
- 245
-
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processorGarcia, Andres / Berekovic, Mladen / Vander Aa, Tom et al. | 2008
- 251
-
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle routerNimmy, Joseph / Ramesh Reddy, C. / Varadarajan, Keshavan / Alle, Mythri / Fell, Alexander / Nandy, S. K. / Narayan, Ranjani et al. | 2008
- 257
-
Loop-oriented metrics for exploring an application-specific architecture design-spaceMbaye, Maria / Belanger, Normand / Savaria, Yvon / Pierre, Samuel et al. | 2008
- 263
-
Rapid estimation of instruction cache hit rates using loop profilingDash, Santanu Kumar / Srikanthan, Thambipillai et al. | 2008
- 269
-
Reducing power consumption of embedded processors through register file partitioning and compiler supportXuan Guan, / Yunsi Fei, et al. | 2008
- 275
-
Lightweight DMA management mechanisms for multiprocessors on FPGATumeo, Antonino / Monchiero, Matteo / Palermo, Gianluca / Ferrandi, Fabrizio / Sciuto, Donatella et al. | 2008
- 281
-
Memory copies in multi-level memory systemsde Langen, Pepijn / Juurlink, Ben et al. | 2008
- 287
-
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decodersAdrsha, Rao / Nandy, S. K. / Narayan, Ranjani et al. | 2008
- 293
-
An FPGA architecture for CABAC decoding in manycore systemsOsorio, Roberto R. / Bruguera, Javier D. et al. | 2008
- 299
-
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filtersGuntoro, Andre / Glesner, Manfred et al. | 2008
- 305
-
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coderMohanty, Basant K. / Meher, Pramod K. et al. | 2008
- 310
-
Author index| 2008
- c1
-
ASAP08 Conference proceedings| 2008
- c1
-
Cover and Frontmatter| 2008
- I
-
Copyright| 2008