A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP$_{3}$, +12 dBm P$_{1{\rm dB}}$, and 15 dB Noise Figure (English)
- New search for: Lee, In-Young
- New search for: Im, Donggu
- New search for: Ko, Jinho
- New search for: Lee, Sang-Gug
- New search for: Lee, In-Young
- New search for: Im, Donggu
- New search for: Ko, Jinho
- New search for: Lee, Sang-Gug
In:
IEEE Journal of Solid-State Circuits
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50
, 10
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2294-2305
;
2015
- Article (Journal) / Electronic Resource
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Title:A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP$_{3}$, +12 dBm P$_{1{\rm dB}}$, and 15 dB Noise Figure
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Contributors:
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Published in:IEEE Journal of Solid-State Circuits ; 50, 10 ; 2294-2305
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Publisher:
- New search for: IEEE
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Publication date:2015-10-01
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Size:3054283 byte
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents – Volume 50, Issue 10
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2225
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Table of Contents| 2015
- 2227
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Introduction to the Special Section on the 2014 Compound Semiconductor Integrated Circuit SymposiumKhalil, Waleed et al. | 2015
- 2228
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170 GHz SiGe-BiCMOS Loss-Compensated Distributed AmplifierTesta, Paolo Valerio / Belfiore, Guido / Paulo, Robert / Carta, Corrado / Ellinger, Frank et al. | 2015
- 2239
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A 60 GHz, 802.11ad/WiGig-Compliant Transceiver for Infrastructure and Mobile Applications in 130 nm SiGe BiCMOSTomkins, Alexander / Poon, Alan / Juntunen, Eric / El-Gabaly, Ahmed / Temkine, Grigori / To, Yat-Loong / Farnsworth, Craig / Tabibiazar, Arash / Fakharzadeh, Mohammad / Jafarlou, Saman et al. | 2015
- 2256
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A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOSKang, Shinwon / Thyagarajan, Siva V. / Niknejad, Ali M. et al. | 2015
- 2268
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A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOSThyagarajan, Siva V. / Kang, Shinwon / Niknejad, Ali M. et al. | 2015
- 2281
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Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency SchemeLee, Dongju / Lee, Minjae et al. | 2015
- 2294
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A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP Formula Not Shown , +12 dBm P Formula Not Shown , and 15 dB Noise FigureIn-Young, L. / Donggu, I. / Jinho, K. / Sang-Gug, L. et al. | 2015
- 2294
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A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP$_{3}$, +12 dBm P$_{1{\rm dB}}$, and 15 dB Noise FigureLee, In-Young / Im, Donggu / Ko, Jinho / Lee, Sang-Gug et al. | 2015
- 2294
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26 dBm IIP[Formula Omitted], +12 dBm P[Formula Omitted], and 15 dB Noise FigureIn-Young Lee et al. | 2015
- 2294
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A 50-450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP , +12 dBm P }, and 15 dB Noise FigureLee, In-Young et al. | 2015
- 2306
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An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOSBhide, Ameya / Alvandpour, Atila et al. | 2015
- 2306
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An 11 GS/s 1.1 GHz Bandwidth Interleaved [delta][sigma] DAC for 60 GHz Radio in 65 nm CMOSAmeya Bhide et al. | 2015
- 2319
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A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch InterpolationKim, Jong-In / Oh, Dong-Ryeol / Jo, Dong-Shin / Sung, Ba-Ro-Saim / Ryu, Seung-Tak et al. | 2015
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A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring AmplifiersLim, Yong / Flynn, Michael P. et al. | 2015
- 2342
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A 0.4 V 63 Formula Not Shown W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching IntegratorYounghyun, Y. / Danbi, C. / Jeongjin, R. et al. | 2015
- 2342
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A 0.4 V 63 [Formula Omitted]W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching IntegratorYounghyun Yoon et al. | 2015
- 2342
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A 0.4 V 63 $\mu$W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching IntegratorYoon, Younghyun / Choi, Danbi / Roh, Jeongjin et al. | 2015
- 2353
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Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew RateYan, Zushu / Mak, Pui-In / Law, Man-Kay / Martins, Rui P. / Maloberti, Franco et al. | 2015
- 2367
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Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking TimeShim, Minseob / Kim, Jungmoon / Jeong, Junwon / Park, Sejin / Kim, Chulwoo et al. | 2015
- 2380
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Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction ModeHong, Sung-Wan / Park, Sang-Hui / Kong, Tae-Hwang / Cho, Gyu-Hyeong et al. | 2015
- 2394
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A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR ApplicationsMargarit, Josep Maria / Vergara, German / Villamayor, Victor / Gutierrez-Alvarez, Raul / Fernandez-Montojo, Carlos / Teres, Lluis / Serra-Graells, Francisco et al. | 2015
- 2406
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A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical TomographyPavia, Juan Mata / Scandini, Mario / Lindner, Scott / Wolf, Martin / Charbon, Edoardo et al. | 2015
- 2419
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A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCsCouniot, Numa / de Streel, Guerric / Botman, Francois / Lusala, Angelo Kuti / Flandre, Denis / Bol, David et al. | 2015
- 2431
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A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change MemoryJin, Dong-Hwan / Kwon, Ji-Wook / Kim, Hyeon-June / Hwang, Sun-Il / Shin, Minchul / Cheon, Junho / Ryu, Seung-Tak et al. | 2015
- 2441
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Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation SchemeYang, Byung-Do et al. | 2015
- 2451
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A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi DecoderChoi, Woong / Kang, Gyuseong / Park, Jongsun et al. | 2015
- 2463
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Correction to “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS”Shahramian, Shayan / Chan Carusone, Anthony et al. | 2015
- 2464
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Corrections to "A \hbox^ 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad"Mohan, P. V. Ananda et al. | 2015
- 2464
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Corrections to "A [Formula Omitted] 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad"P V Ananda Mohan et al. | 2015
- 2464
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Corrections to “A $\hbox{0.02 mm}^{2}$ 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad”Mohan, P. V. Ananda / Zhao, Yaohua / Mak, Pui-In / Martins, Rui P. / Maloberti, Franco et al. | 2015
- 2465
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