Zero capacitor embedded memory technology for system on chip (English)
- New search for: Okhonin, S.
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- New search for: Okhonin, S.
- New search for: Fazan, P.
- New search for: Jones, M.-E.
In:
2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)
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xxi-xxv
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2005
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- Conference paper / Electronic Resource
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Title:Zero capacitor embedded memory technology for system on chip
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Publisher:
- New search for: IEEE
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Publication date:2005-01-01
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Size:346486 byte
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
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Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memoryKung-Hong Lee, / Shih-Chen Wang, / Ya-Chin King, et al. | 2005
- 9
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A novel CMOS compatible embedded nonvolatile memory with zero process adderBreitwisch, M.J. / Lam, C.H. / Johnson, J.B. / Mittl, S.W.W. / Zhu, J.W. et al. | 2005
- 13
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Embedded OTP fuse in CMOS logic processChing-Yuan Lin, / Chung-Hung Lin, / Chien-Hung Ho, / Wei-Wu Liao, / Shu-Yueh Lee, / Ming-Chou Ho, / Shin-Chen Wang, / Shih-Chan Huang, / Yuan-Tai Lin, / Charles Ching-Hsiang Hsu, et al. | 2005
- 16
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Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding techniqueMeng-Fan Chang, / Kuei-Ann Wen, / Ding-Ming Kwai, et al. | 2005
- 22
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A nor-type MLC ROM with novel sensing scheme for embedded applicationsStar Sung, / Chang, T. / Juei Lung Chen, et al. | 2005
- 29
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Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applicationsLi, S.C. / Su, J.P. / Wu, T.-H. / Lee, J.M. / Shu, M.F. et al. | 2005
- 35
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A Novel Single Poly-Silicon EEROM Using Trench Floating GateWu, M.-Y. / Feng, S.-C. / King, Y.-C. / IEEE Computer Society et al. | 2005
- 35
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A novel single poly-silicon EEPROM using trench floating gateMeng-Yi Wu, / Shin-Chang Feng, / Ya-Chin King, et al. | 2005
- 38
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An investigation into three-level ferroelectric memoryRaiter, K.R. / Cockburn, B.F. et al. | 2005
- 47
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A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capabilityLines, V. / McKenzie, R. / Hak-June Oh, / Hong-Beom Pyeon, / Dunn, M. / Palapar, S. / Coleman, S. / Nyasulu, P. / Mai, T. / Pike, S. et al. | 2005
- 52
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A high speed BIST architecture for DDR-SDRAM testingSheng-Chih Shen, / Hung-Ming Hsu, / Yi-Wei Chang, / Kuen-Jong Lee, et al. | 2005
- 58
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A programmable built-in self-test for embedded DRAMsBanerjee, S. / Chowdhury, D.R. / Bhattacharya, B.B. et al. | 2005
- 67
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Full-speed field programmable memory BIST supporting multi-level loopingXiaogang Du, / Mukherjee, N. / Wu-Tung Cheng, / Reddy, S.M. et al. | 2005
- 72
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FSM-based programmable memory BIST with macro commandPo-Chang Tsai, / Sying-Jyan Wang, / Feng-Ming Chang, et al. | 2005
- 78
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A DFT Architecture for a Dynamic Fault Model of the Embedded Mask ROM of SOCLee, Y.-H. / Jan, Y.-G. / Shen, J.-J. / Tzeng, S.-W. / Chuang, M.-H. / Lin, J.-Y. / IEEE Computer Society et al. | 2005
- 78
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DFT architecture for a dynamic fault model of the embedded mask ROM of SOCYang-Han Lee, / Yih-Guang Jan, / Jei-Jung Shen, / Shian-Wei Tzeng, / Ming-Hsueh Chuang, / Jheng-Yao Lin, et al. | 2005
- 83
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A complete memory address generator for scan based March algorithmsWei-Lun Wang, / Kuen-Jong Lee, et al. | 2005
- 89
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Software based in-system memory test for highly available systemsSingh, A. / Bose, D. / Darisala, S. et al. | 2005
- 97
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A systematic approach to reducing semiconductor memory test time in mass productionJen-Chieh Yeh, / Shyr-Fen Kuo, / Cheng-Wen Wu, / Chih-Tsun Huang, / Chao-Hsun Chen, et al. | 2005
- 103
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Impact of stresses on the fault coverage of memory testsHamdioui, S. / Al-Ars, Z. / van de Goor, A.J. / Wadsworth, R. et al. | 2005
- 109
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DFT techniques for memory macro with built-in ECCKushida, K. / Otsuka, N. / Hirabayashi, O. / Takeyama, T. et al. | 2005
- 115
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An error detection and correction scheme for RAMs with partial-write functionJin-Fu Li, / Yu-Jane Huang, et al. | 2005
- 121
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A BIRA algorithm for embedded memories with 2D redundancyShyue-Kung Lu, / Yu-Cheng Tsai, / Shih-Chang Huang, et al. | 2005
- 129
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Distributed data-retention power gating techniques for column and row co-controlled embedded SRAMChung-Hsien Hua, / Tung-Shuan Cheng, / Wei Hwang, et al. | 2005
- 135
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A low-power SRAM design using quiet-bitline architectureShin-Pao Cheng, / Shi-Yu Huang, et al. | 2005
- 140
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Measurement and characterization of 6T SRAM cell currentChing-Hua Hsiao, / Ding-Ming Kwai, et al. | 2005
- 146
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Reliability enhancement of CMOS SRAMsChin-Long Wey, / Meng-Yao Liu, / Shaolei Quan, et al. | 2005
- 153
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Author index| 2005
- c1
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2005 IEEE International Workshop on Memory Technology, Design, and Testing - Cover| 2005
- iv
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2005 IEEE International Workshop on Memory Technology, Design, and Testing - Copyright Page| 2005
- ix
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Organizing Committee| 2005
- v
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2005 IEEE International Workshop on Memory Technology, Design, and Testing - Table of Contents| 2005
- viii
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Foreword| 2005
- x
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Program Committee| 2005
- xi
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list-reviewer| 2005
- xii
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Test Technology Technical Council| 2005
- xv
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Advanced simulation technology and its application in memory design and verificationMcGaughy, B. / Wuensche, S. / Hung, K.K. et al. | 2005
- xxi
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Zero capacitor embedded memory technology for system on chipOkhonin, S. / Fazan, P. / Jones, M.-E. et al. | 2005
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2005 IEEE International Workshop on Memory Technology, Design and Testing| 2005