Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip (English)
- New search for: Cheung, Eric
- New search for: Hsieh, Harry
- New search for: Balarin, Felice
- New search for: Cheung, Eric
- New search for: Hsieh, Harry
- New search for: Balarin, Felice
In:
2007 IEEE International High Level Design Validation and Test Workshop
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37-44
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2007
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ISBN:
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ISSN:
- Conference paper / Electronic Resource
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Title:Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2007-11-01
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Size:631906 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Session 1: Multiprocessors I| 2007
- 3
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Reliable network-on-chip based on generalized de Bruijn graphHosseinabady, Mohammad / Kakoee, Mohammad Reza / Mathew, Jimson / Pradhan, Dhiraj K. et al. | 2007
- 11
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Improving feasible interactions among multiple processesRamineni, Kiran / Harris, Ian G. / Verma, Shireesh et al. | 2007
- 19
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Session 2: Multiprocessors 11| 2007
- 21
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Framework for fast and accurate performance simulation of multiprocessor systemsCheung, Eric / Hsieh, Harry / Balarin, Felice et al. | 2007
- 29
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Automatic TLM generation for C-Based MPSoC designLucky Lo Chi Yu Lo, / Samar Abdi, et al. | 2007
- 37
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Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chipCheung, Eric / Hsieh, Harry / Balarin, Felice et al. | 2007
- 45
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Session 3: Invited Session: Post-Silicon Validation| 2007
- 47
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Post-silicon verification methodology on Sun’s UItraSPARC T2Kumar, Jai / Ahlschlager, Catherine / Isberg, Peter et al. | 2007
- 48
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Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processorsKapoor, Shakti et al. | 2007
- 53
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Intel’s Post Silicon functional validation approachTommy, Bojan / Igor, Frumkin / Robert, Mauri et al. | 2007
- 57
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Session 4: Debug| 2007
- 59
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Bug analysis and corresponding error models in real designsTao Lv, / Tong Xu, / Yang Zhao, / Huawei Li, / Xiaowei Li, et al. | 2007
- 65
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Automatic error diagnosis and correction for RTL designsKai-hui Chang, / Ilya Wagner, / Bertacco, Valeria / Markov, Igor L. et al. | 2007
- 73
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Bridging RTL and gate: correlating different levels of abstraction for design debuggingEric Cheung, / Xi Chen, / Furshing Tsai, / Yu-Chin Hsu, / Harry Hsieh, et al. | 2007
- 81
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Session 5: Test generation| 2007
- 83
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Model-driven test generation for system level validationMathaikutty, Deepak A. / Sumit Ahuja, / Ajit Dingankar, / Sandeep Shukla, et al. | 2007
- 91
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Towards RTL test generation from SystemC TLM specificationsMingsong Chen, / Prabhat Mishra, / Dhrubajyoti Kalita, et al. | 2007
- 97
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A novel formal approach to generate high-level test vectors without ILP and SAT solversAlizadeh, Bijan / Fujita, Masahiro et al. | 2007
- 105
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Session 6: Formal verification| 2007
- 107
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Hierarchical cache coherence protocol verification one level at a time through assume guaranteeXiaofang Chen, / Yu Yang, / Delisi, Michael / Ching-Tsun Chou, et al. | 2007
- 115
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Formal model construction using HDL simulation semanticsBuck, Joseph / Wang, Dong / Zhu, Yunshan et al. | 2007
- 123
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An approach for computing the initial state for retimed synchronous sequential circuitsChabini, Noureddine / Wolf, Wayne et al. | 2007
- 131
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Session 7: invited session: high level design| 2007
- 133
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Circuit design and verication with Esterel v7 and Esterel StudioBerry, Gerard et al. | 2007
- 137
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FFT Compiler: from math to efficient hardware HLDVT invited short paperMilder, Peter A. / Franchetti, Franz / Hoe, James C. / Puschel, Markus et al. | 2007
- 140
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Transactors for parallel hardware and software co-designAsanovic, Krste et al. | 2007
- 143
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Session 8: coverage directed validation| 2007
- 145
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Functional coverage measurements and results in post-Silicon validation of Core™2 duo familyBojan, Tommy / Aguilar Arreola, Manuel / Shlomo, Eran / Shachar, Tal et al. | 2007
- 151
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Coverage-directed test generation through automatic constraint extractionOnur Guzey, / Wang, Li-C. et al. | 2007
- 159
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Automatic generation of functional coverage models from CTLVerma, Shireesh / Harris, Ian G. / Ramineni, Kiran et al. | 2007
- 165
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Session 9 panel: unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test| 2007
- 167
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Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production testKakkar, Sunil / Bergeron, Janick / Bailey, Brian / Foster, Harry / Harris, Ian et al. | 2007
- 169
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Session 10: Embedded Systems| 2007
- 171
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Automating the IEEE std. 1500 compliance verification for embedded coresBenso, A. / Di Carlo, S. / Prinetto, P. / Bosio, A. et al. | 2007
- 179
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Validating the dependability of embedded systems through fault injection by means of loadable kernel modulesMurciano, Marco / Violante, Massimo et al. | 2007
- 187
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AME: an abstract middleware environment for validating networked embedded systems applicationsFummi, F. / Perbellini, G. / Quaglia, D. / Vinco, S. et al. | 2007
- 195
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Author index| 2007
- i
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Proceedings| 2007
- ix
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Keynote| 2007
- v
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Table of Contents| 2007