Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond (English)
- New search for: Park, C.
- New search for: Lee, H.
- New search for: Ching, C.
- New search for: Ahn, J.
- New search for: Wang, R.
- New search for: Pakala, M.
- New search for: Kang, S. H.
- New search for: Park, C.
- New search for: Lee, H.
- New search for: Ching, C.
- New search for: Ahn, J.
- New search for: Wang, R.
- New search for: Pakala, M.
- New search for: Kang, S. H.
In:
2018 IEEE Symposium on VLSI Technology
;
185-186
;
2018
-
ISBN:
-
ISSN:
- Conference paper / Electronic Resource
-
Title:Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond
-
Contributors:Park, C. ( author ) / Lee, H. ( author ) / Ching, C. ( author ) / Ahn, J. ( author ) / Wang, R. ( author ) / Pakala, M. ( author ) / Kang, S. H. ( author )
-
Published in:2018 IEEE Symposium on VLSI Technology ; 185-186
-
Publisher:
- New search for: IEEE
-
Publication date:2018-06-01
-
Size:529207 byte
-
ISBN:
-
ISSN:
-
DOI:
-
Type of media:Conference paper
-
Type of material:Electronic Resource
-
Language:English
-
Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 3
-
Memory Technology: The Core to Enable Future Computing SystemsDeBoer, Scott et al. | 2018
- 7
-
Revolutionizing Cancer Genomic Medicine by AI and Supercomputer with Big DataMiyano, Satoru et al. | 2018
- 15
-
Shaping circuit environment to face the thermal challenge Innovative technologies from low to high power electronicsCoudrain, P. / Colonna, J.-P. / Collin, L.-M. / Prieto, R. / Frechette, L.G. / Barrau, J. / Savelli, G. / Vivet, P. / Struss, Q. / Widiez, J. et al. | 2018
- 17
-
Thermal Management Research – from Power Electronics to PortablesJung, Ki Wook / Zhang, Chi / Liu, Tanya / Asheghi, Mehdi / Goodson, Kenneth E. et al. | 2018
- 19
-
Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping PointsZhou, Chen / Wong, Richard / Wen, Shi-Jie / Kim, Chris H. et al. | 2018
- 21
-
Low Thermal Budget Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Near Ideal Subthreshold SwingKuo, Po-Yi / Chang, Chien-Min / Liu, Po-Tsun et al. | 2018
- 25
-
Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and LinearityLi, Y. / Kim, S. / Sun, X. / Solomon, P. / Gokmen, T. / Tsai, H. / Koswatta, S. / Ren, Z. / Mo, R. / Yeh, C. C. et al. | 2018
- 27
-
Analog Spike Processing with High Scalability and Low Energy Consumption Using Thermal Degree of Freedom in Phase Transition MaterialsYajima, T. / Nishimura, T. / Toriumi, A. et al. | 2018
- 29
-
An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AIKuo, J. L. / Chen, H. W. / Hsieh, E. R. / Chung, Steve S. / Chen, T. P. / Huang, S. A. / Chen, J. / Cheng, Osbert et al. | 2018
- 31
-
Novel In-Memory Matrix-Matrix Multiplication with Resistive Cross-Point ArraysLiao, Yan / Wu, Huaqiang / Wan, Weier / Zhang, Wenqiang / Gao, Bin / Philip Wong, H.-S. / Qian, He et al. | 2018
- 35
-
Sensors and related devices for IoT, medicine and s mart-livingErnst, T. / Guillemaud, R. / Mailley, P. / Polizzi, J.P. / Koenig, A. / Boisseau, S. / Pauliac-Vaujour, E. / Plantier, C. / Delapierre, G. / Saoutieff, E. et al. | 2018
- 37
-
Development of a Multisite, Closed-loop Neuromodulator for the Theranosis of Neural Degenerative DiseasesChen, Hsin / Chang, Yen-Chung / Yeh, Shih-Rung / Hsieh, Chih-Cheng / Tang, Kea-Tiong / Hsieh, Ping-Hsuan / Liao, Yu-Te / Perumel, Ramesh / Chuang, Ji-Feng / Chang, Ching-Chih et al. | 2018
- 39
-
High Performance High Density Gas-FET Array in Standard CMOSYu, Qian / Zhong, Xiaopeng / Boussaid, Farid / Bermak, Amine / Tsui, CY et al. | 2018
- 41
-
High-sensitivity and low-power inertial MEMS-on-CMOS sensors using low-temperature-deposited poly-SiGe film for the IoT eraTomizawa, Hideyuki / Kurui, Yoshihiko / Akita, Ippei / Fujimoto, Akira / Saito, Tomohiro / Kojima, Akihiro / Shibata, Hideki et al. | 2018
- 45
-
A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm NodeTang, Y.-T / Su, C.-J. / Wang, Y.-S. / Kao, K.-H. / Wu, T.-L. / Sung, P.-J. / Hou, F.-J. / Wang, C.-J. / Yeh, M.-S. / Lee, Y.-J. et al. | 2018
- 47
-
First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate StackLuc, Q. H. / Fan-Chiang, C. C. / Huynh, S. H. / Huang, P. / Do, H. B. / Ha, M. T. H. / Jin, Y. D. / Nguyen, T. A. / Zhang, K. Y. / Wang, H. C. et al. | 2018
- 49
-
Response Speed of Negative Capacitance FinFETsKwon, Daewoong / Liao, Yu-Hung / Lin, Yen-Kai / Duarte, Juan Pablo / Chatterjee, Korok / Tan, Ava J. / Yadav, Ajay K. / Hu, Chenming / Krivokapic, Zoran / Salahuddin, Sayeef et al. | 2018
- 51
-
Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETsObradovic, B. / Rakshit, T. / Hatcher, R. / Kittl, J. A. / Rodder, M. S. et al. | 2018
- 53
-
Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel EffectZhou, Hong / Kwon, Daewoong / Sachid, Angada B. / Liao, Yuhung / Chatterjee, Korok / Tan, Ava J. / Yadav, Ajay K. / Hu, Chenming / Salahuddin, Sayeef et al. | 2018
- 59
-
True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion BreakJeong, WC / Maeda, S. / Lee, HJ / Lee, KW / Lee, TJ / Park, DW / Kim, BS / Do, JH / Fukai, T / Kwon, DJ et al. | 2018
- 61
-
Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETsLee, Rinus T.P. / Petrov, N. / Kassim, J. / Gribelyuk, M. / Yang, J. / Cao, L. / Yeap, K.B. / Shen, T. / Zainuddin, A. N. / Chandrashekar, A. et al. | 2018
- 63
-
From Memory to Sensor: ultra-Low Power and High Selectivity Hydrogen Sensor Based on ReRAM TechnologyWei, Zhiqiang / Homma, Kazunari / Katayama, Koji / Kawai, Ken / Fujii, Satoru / Naitoh, Yasuhisa / Shima, Hisashi / Akinaga, Hiroyuki / Ito, Satoru / Yoneda, Shinichi et al. | 2018
- 65
-
Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM designed for compatibility with 0x node embedded LLC applicationsJan, Guenole / Thomas, Luc / Le, Son / Lee, Yuan-Jen / Liu, Huanlong / Zhu, Jian / Iwata-Harms, Jodi / Patel, Sahil / Tong, Ru-Ying / Sundar, Vignesh et al. | 2018
- 69
-
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliabilityVandooren, A. / Franco, J. / Parvais, B. / Wu, Z. / Witters, L. / Walke, A. / Li, W. / Peng, L. / Desphande, V. / Bufler, F.M. et al. | 2018
- 71
-
An over 120 dB wide-dynamic-range 3.0 μm pixel image sensor with in-pixel capacitor of 41.7 fF/um2 and high reliability enabled by BEOL 3D capacitor processTakase, M. / Isono, S. / Tomekawa, Y. / Koyanagi, T. / Tokuhara, T. / Harada, M. / Inoue, Y. et al. | 2018
- 73
-
Selective Pore-Sealing of Highly Porous Ultralow-k dielectrics for ULSI Interconnects by Cyclic Initiated Chemical Vapor Deposition ProcessYoon, Seong Jun / Pak, Kwanyong / Ahn, Hyun Jun / Yoon, Alexander / Im, Sung Gap / Jin Cho, Byung et al. | 2018
- 75
-
Performance and Reliability of a Fully Integrated 3D Sequential TechnologyTsiara, A. / Garros, X. / Brunet, L. / Batude, P. / Fenouillet-Beranger, C. / Triantopoulos, K. / Casse, M. / Vinet, M. / Gaillard, F. / Ghibaudo, G. et al. | 2018
- 77
-
Metal/P-type GeSn Contacts with Specific Contact Resistivity down to 4.4×10−10 Ω-cm2Wu, Ying / Wang, Wei / Masudy-Panah, Saeid / Li, Yang / Han, Kaizhen / He, Liuhuiquan / Zhang, Zheng / Lei, Dian / Xu, Shengqiang / Kang, Yuye et al. | 2018
- 81
-
Multiple Workfunction High Performance FinFETs for Ultra-low Voltage OperationTogo, M. / Asra, R. / Balasubramaniam, P. / Zhang, X. / Yu, H. / Yamaguchi, S. / Geiss, E. / Yang, H. S. / Cohen, B. / Lo, H-C. et al. | 2018
- 83
-
An In-depth Study of High-Performing Strained Germanium Nanowires pFETsMitard, J. / Jang, D. / Eneman, G. / Arimura, H. / Parvais, B. / Richard, O. / Van Marcke, P. / Witters, L. / Capogreco, E. / Bender, H. et al. | 2018
- 85
-
Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire TechnologyHellings, G. / Mertens, H. / Subirats, A. / Simoen, E. / Schram, T. / Ragnarsson, L.-A. / Simicic, M. / Chen, S.-H. / Parvais, B. / Boudier, D. et al. | 2018
- 87
-
Leakage aware Si/SiGe CMOS FinFET for low power applicationsTsutsui, Gen / Durfee, Curtis / Wang, Miaomiao / Konar, Aniruddha / Wu, Heng / Mochizuki, Shogo / Bao, Ruqiang / Bedell, Stephen / Li, Juntao / Zhou, Huimei et al. | 2018
- 89
-
First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETsChung, Wonil / Si, Mengwei / Shrestha, Pragya R. / Campbell, Jason P. / Cheung, Kin P. / Ye, Peide D. et al. | 2018
- 93
-
10μW/cm2-Class High Power Density Planar Si-Nanowire Thermoelectric Energy Harvester Compatible with CMOS-VLSI TechnologyTomita, M. / Oba, S. / Himeda, Y. / Yamato, R. / Shima, K. / Kumada, T. / Xu, M. / Takezawa, H. / Mesaki, K. / Tsuda, K. et al. | 2018
- 95
-
A low-power and high-speed True Random Number Generator using generated RTNBrown, James / Gao, Rui / Ji, Zhigang / Chen, Jiezhi / Wu, Jixuan / Zhang, Jianfu / Zhou, Bo / Shi, Qi / Crowford, Jacob / Zhang, Weidong et al. | 2018
- 97
-
Ultrahigh-Sensitive and CMOS Compatible ISFET Developed in BEOL of Industrial UTBB FDSOIAyele, Getenet Tesega / Monfray, Stephane / Ecoffey, Serge / Boeuf, Frederic / Bon, Romain / Cloarec, Jean-Pierre / Drouin, Dominique / Souifi, Abdelkader et al. | 2018
- 99
-
RX-PUF: Low Power, Dense, Reliable, and Resilient Physically Unclonable Functions Based on Analog Passive RRAM Crossbar ArraysMahmoodi, Mohammad Reza / Nili, Hussein / Strukov, Dmitri. B. et al. | 2018
- 103
-
A Methodology to Improve Linearity of Analog RRAM for Neuromorphic ComputingWu, Wei / Wu, Huaqiang / Gao, Bin / Yao, Peng / Zhang, Xiang / Peng, Xiaochen / Yu, Shimeng / Qian, He et al. | 2018
- 105
-
Non-Volatile Ternary Content Addressable Memory (TCAM) with Two HfO2/Al2O3/GeOx/Ge MOS DiodesZhang, Yi / Chen, Bing / Dong, Wenfeng / Liu, Wei / Xu, Shun / Cheng, Ran / Lee, Shiuh-Wuu / Zhao, Yi et al. | 2018
- 107
-
Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAMJiang, Zizhen / Qin, Shengjun / Li, Haitong / Fujii, Shosuke / Lee, Dongjin / Wong, Simon / Wong, H.-S. Philip et al. | 2018
- 109
-
5x Reliability Enhanced 40nm TaOx Approximate-ReRAM with Domain-Specific Computing for Real-time Image Recognition of IoT Edge DevicesYamaga, Yusuke / Deguchi, Yoshiaki / Fukuyama, Shouhei / Takeuchi, Ken et al. | 2018
- 113
-
Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability EvaluationYan, Jhih-Yang / Chung, Chia-Che / Jan, Sun-Rong / Lin, H. H. / Wan, W. K. / Yang, M.-T. / Liu, C. W. et al. | 2018
- 115
-
Differentiated Performance and Reliability Enabled by Multi-Work Function Solution in RMG Silicon and SiGe MOSFETsBao, R. / Southwick, R. G. / Zhou, H. / Lee, C. H. / Linder, B. P. / Ando, T. / Guo, D. / Jagannathan, H. / Narayanan, V. et al. | 2018
- 117
-
Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm NodeXue, Lin / Ching, Chi / Kontos, Alex / Ahn, Jaesoo / Wang, Xiaodong / Whig, Renu / Tseng, Hsin-wei / Howarth, James / Hassan, Sajjad / Chen, Hao et al. | 2018
- 119
-
Dependence of Reliability of Ferroelectric HfZrOx on Epitaxial SiGe Film with Various Ge ContentChen, Kuen-Yi / Huang, Yen-Hua / Kao, Ruei-Wen / Lin, Yan-Xiao / Wu, Yung-Hsien et al. | 2018
- 121
-
Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product ReliabilitySagong, H. C. / Choi, K. / Kim, J. / Jeong, T. / Choe, M. / Shim, H. / Kim, W. / Park, J. / Shin, S. / Pae, S. et al. | 2018
- 125
-
All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS TechnologyHutin, L. / Bourdet, L. / Bertrand, B. / Corna, A. / Bohuslavskyi, H. / Amisse, A. / Crippa, A. / Maurand, R. / Barraud, S. / Urdampilleta, M. et al. | 2018
- 127
-
High-Density and Fault-Tolerant Cu Atom Switch Technology Toward 28nm-node Nonvolatile Programmable LogicNebashi, R. / Banno, N. / Miyamura, M. / Tsuji, Y. / Morioka, A. / Bai, X. / Okamoto, K. / Iguchi, N. / Numata, H. / Hada, H. et al. | 2018
- 129
-
A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory ApplicationsJerry, M. / Aziz, A. / Ni, K. / Datta, S. / Gupta, S. K. / Shukla, N. et al. | 2018
- 131
-
A Circuit Compatible Accurate Compact Model for Ferroelectric-FETsNi, Kai / Jerry, Matthew / Smith, Jeffrey A. / Datta, Suman et al. | 2018
- 133
-
Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETsAlian, Alireza / Kazzi, Salim El / Verhulst, Anne / Milenin, Alexey / Pinna, Nicolo / Ivanov, Tsvetan / Lin, Dennis / Mocuta, Dan / Collaert, Nadine et al. | 2018
- 137
-
Improving Performance, Power, and Area by Optimizing Gear Ratio of Gate-Metal Pitches in Sub-10nm Node CMOS DesignsBan, Yongchan / Zhu, Xuelian / Petykiewicz, Jan / Zeng, Jia et al. | 2018
- 139
-
Achieving High-Scalability Negative Capacitance FETs with Uniform Sub-35 mV/dec Switch Using Dopant-Free Hafnium Oxide and Gate StrainFan, Chia-Chi / Cheng, Chun-Hu / Tu, Chun-Yuan / Liu, Chien / Chen, Wan-Hsin / Chang, Tun-Jen / Chang, Chun-Yen et al. | 2018
- 141
-
The Complementary FET (CFET) for CMOS scaling beyond N3Ryckaert, J. / Schuddinck, P. / Weckx, P. / Bouche, G. / Vincent, B. / Smith, J. / Sherazi, Y. / Mallik, A. / Mertens, H. / Demuynck, S. et al. | 2018
- 143
-
Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard CellsBardon, M. Garcia / Sherazi, Y. / Jang, D. / Yakimets, D. / Schuddinck, P. / Baert, R. / Mertens, H. / Mattii, L. / Parvais, B. / Mocuta, A. et al. | 2018
- 147
-
Enabling CMOS Scaling Towards 3nm and BeyondMocuta, A. / Weckx, P. / Demuynck, S. / Radisic, D. / Oniki, Y. / Ryckaert, J. et al. | 2018
- 149
-
Smart scaling technology for advanced FinFET nodeKye, Jongwook / Kim, Hoonki / Lim, Jinyoung / Lee, Seungyoung / Jung, Jonghoon / Song, Taejoong et al. | 2018
- 151
-
Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write AssistKim, Daeyeon / Wiedemer, Jami / Kolar, Pramod / Shrivastava, Ayush / Shah, Jinal / Nalam, Satyanand / Baek, Gwanghyeon / Wang, Xiaofei / Guo, Zheng / Karl, Eric et al. | 2018
- 153
-
Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixingAndrieu, F. / Pirro, L. / Berthelon, R. / Morgan, J. / Cibrario, G. / Wiatr, M. / Hoentschel, J. / Vinet, M. et al. | 2018
- 157
-
Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platformLiao, P. H. / Kuo, M. H. / Tien, C. W. / Chang, Y. L. / Hong, P. Y. / George, T. / Lin, H. C. / Li, P. W. et al. | 2018
- 159
-
A Near- & Short-Wave IR Tunable InGaAs Nanomembrane PhotoFET on Flexible Substrate for Lightweight and Wide-Angle Imaging ApplicationsLi, Yida / Alian, Alireza / Huang, Li / Ang, Kah Wee / Lin, Dennis / Mocuta, Dan / Collaert, Nadine / Thean, Aaron V-Y et al. | 2018
- 161
-
Integration of 2D Black Phosphorus Phototransistor and Silicon Photonics Waveguide System Towards Mid-Infrared On-Chip Sensing ApplicationsHuang, Li / Dong, Bowei / Guo, Xin / Chang, Yuhua / Chen, Nan / Huang, Xin / Wang, Hong / Lee, Chengkuo / Ang, Kah-Wee et al. | 2018
- 163
-
Next-generation Fundus Camera with Full Color Image Acquisition in 0-lx Visible Light by 1.12-micron Square Pixel, 4K, 30-fps BSI CMOS Image Sensor with Advanced NIR Multi-spectral Imaging SystemSumi, Hirofumi / Takehara, Hironari / Miyazaki, Shunsuke / Shirahige, Daiki / Sasagawa, Kiyotaka / Tokuda, Takashi / Watanabe, Yoshihiro / Kishi, Norimasa / Ohta, Jun / Ishikawa, Masatoshi et al. | 2018
- 165
-
InGaAs-on-Insulator MOSFETs Featuring Scaled Logic Devices and Record RF PerformanceZota, C. B. / Convertino, C. / Deshpande, V. / Merkle, T. / Sousa, M. / Caimi, D. / Czomomaz, L. et al. | 2018
- 169
-
Neuromorphic Technology Based on Charge Storage Memory DevicesLee, Sung-Tae / Lim, Suhwan / Choi, Nagyong / Bae, Jong-Ho / Kim, Chul-Heung / Lee, Soochang / Lee, Dong Hwan / Lee, Tackhwi / Chung, Sungyong / Park, Byung-Gook et al. | 2018
- 171
-
Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial IntelligenceDou, Chun-Meng / Chen, Wei-Hao / Xue, Cheng-Xin / Lin, Wei-Yu / Lin, Wei-En / Li, Jun-Yi / Lin, Huan-Ting / Chang, Meng-fan et al. | 2018
- 173
-
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural NetworksJiang, Zhewei / Yin, Shihui / Seok, Mingoo / Seo, Jae-sun et al. | 2018
- 175
-
A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network ArchitectureMochida, Reiji / Kouno, Kazuyuki / Hayata, Yuriko / Nakayama, Masayoshi / Ono, Takashi / Suwa, Hitoshi / Yasuhara, Ryutaro / Katayama, Koji / Mikawa, Takumi / Gohou, Yasushi et al. | 2018
- 177
-
A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence ApplicationLue, Hang-Ting / Chen, Weichen / Chang, Hung-Sheng / Wang, Keh-Chung / Lu, Chih-Yuan et al. | 2018
- 181
-
Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT ApplicationLee, Yong Kyu / Song, Yoonjong / Kim, JooChan / Oh, SeChung / Bae, Byoung-Jae / Lee, SangHumn / Lee, JungHyuk / Pi, UngHwan / Seo, Boyoung / Jung, Hyunsung et al. | 2018
- 183
-
22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic ImmunityLee, K. / Yamane, K. / Noh, S. / Naik, V. B. / Yang, H. / Jang, S. H. / Kwon, J. / Behin-Aein, B. / Chao, R. / Lim, J. H. et al. | 2018
- 185
-
Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and BeyondPark, C. / Lee, H. / Ching, C. / Ahn, J. / Wang, R. / Pakala, M. / Kang, S. H. et al. | 2018
- 187
-
Rare-Failure Oriented STT-MRAM Technology OptimizationXu, Nuo / Chen, Fan / Apalkov, Dmytro / Qi, Weiyi / Wang, Jing / Jiang, Zhengping / Choi, Woosung / Kim, Dae Sin et al. | 2018
- 191
-
Significant Performance Enhancement of UTB GeOI pMOSFETs by Advanced Channel Formation TechnologiesChang, W. H. / Irisawa, T. / Ishii, H. / Hattori, H. / Uchida, N. / Maeda, T. et al. | 2018
- 193
-
First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETsCapogreco, E. / Witters, L. / Arimura, H. / Sebaai, F. / Porret, C. / Hikavyy, A. / Loo, R. / Milenin, A. P. / Eneman, G. / Favia, P. et al. | 2018
- 195
-
Hole mobility enhancement in extremely-thin-body strained GOI and SGOI pMOSFETs by improved Ge condensation methodJo, K.-W. / Kim, W.-K. / Takenaka, M. / Takagi, S. et al. | 2018
- 197
-
GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•sLei, Dian / Han, Kaizhen / Lee, Kwang Hong / Huang, Yi-Chiau / Wang, Wei / Yadav, Sachin / Kumar, Annie / Wu, Ying / Heliu, Huiquan / Xu, Shengqiang et al. | 2018
- 201
-
Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC DesignKang, Ho-Jung / Choi, Nagyong / Lee, Dong Hwan / Lee, Tackhwi / Chung, Sungyong / Bae, Jong-Ho / Park, Byung-Gook / Lee, Jong-Ho et al. | 2018
- 203
-
First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devicesDelhougne, R. / Arreghini, A. / Rosseel, E. / Hikavyy, A. / Vecchio, E. / Zhang, L. / Pak, M. / Nyns, L. / Raymaekers, T. / Jossart, N. et al. | 2018
- 205
-
High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable MemoryYeh, C. W. / Chien, W. C. / Bruce, R. L. / Cheng, H. Y. / Kuo, I. T. / Yang, C. H. / Ray, A. / Miyazoe, H. / Kim, W. / Carta, F. et al. | 2018
- 207
-
Te-based binary OTS selectors with excellent selectivity (>105), endurance (>108) and thermal stability (>450°C)Yoo, Jongmyung / Koo, Yunmo / Chekol, Solomon Amsalu / Park, Jaehyuk / Song, Jeonghwan / Hwang, Hyunsang et al. | 2018
- 209
-
Half-threshold bias Ioff reduction down to nA range of thermally and electrically stable high-performance integrated OTS selector, obtained by Se enrichment and N-doping of thin GeSe layersAvasarala, Naga Sruti / Donadio, G. L. / Witters, T. / Opsomer, K. / Govoreanu, B. / Fantini, A. / Clima, S. / Oh, H. / Kundu, S. / Devulder, W. et al. | 2018
- 213
-
Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU ApplicationsKim, H.-J. / Choi, B.H. / Lee, Y.H. / Ahn, J.H. / Bang, Y.S. / Lim, Y.D. / Do, J.H. / Jung, J.H. / Song, T.J. / Yasuda-Masuoka, Y. et al. | 2018
- 215
-
A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance ApplicationsLo, H.C. / Choi, D. / Hu, Y. / Shen, Y. / Qi, Y. / Peng, J. / Zhou, D. / Mohan, M. / Yong, C. / Zhan, H. et al. | 2018
- 217
-
8LPP Logic Platform Technology for Cost-Effective High Volume ManufacturingRhee, Hwasung / Kim, Ilryong / Jeong, Jaehun / Son, Nakjin / Hong, Heebum / Cho, Sungil / Park, Yongmin / Kim, Dongwoo / Choi, Yunki / Ahn, Jeonghoon et al. | 2018
- 219
-
High Performance Mobile SoC Productization with Second-Generation 10-nm FinFET Technology and Extension to 8-nm ScalingYuan, Jun / Rim, Ken / Chen, Ying / Cai, Ming / Suh, Youseok / Choi, Jihong / Deng, Jie / Bao, Jerry / Song, Zhimin / Ge, Lixin et al. | 2018
- 221
-
Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/ORakowski, M. / Ban, Y. / De Heyn, P. / Pantano, N. / Snyder, B. / Balakrishnan, S. / Van Huylenbroeck, S. / Bogaerts, L. / Demeurisse, C. / Inoue, F. et al. | 2018
- i
-
VLSI Technology 2018 Breaker Page| 2018
- i
-
VLSI Technology 2018 Preface| 2018
- i
-
VLSI Technology 2018 Foreword| 2018