Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs (English)
- New search for: Rhee, H.S.
- New search for: Bae, G.J.
- New search for: Choe, T.H.
- New search for: Kim, S.S.
- New search for: Song, S.
- New search for: Lee, N.I.
- New search for: Fujihara, K.
- New search for: Kang, H.K.
- New search for: Moon, J.T.
- New search for: Rhee, H.S.
- New search for: Bae, G.J.
- New search for: Choe, T.H.
- New search for: Kim, S.S.
- New search for: Song, S.
- New search for: Lee, N.I.
- New search for: Fujihara, K.
- New search for: Kang, H.K.
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In:
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
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61-62
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2001
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ISBN:
- Conference paper / Electronic Resource
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Title:Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs
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Contributors:Rhee, H.S. ( author ) / Bae, G.J. ( author ) / Choe, T.H. ( author ) / Kim, S.S. ( author ) / Song, S. ( author ) / Lee, N.I. ( author ) / Fujihara, K. ( author ) / Kang, H.K. ( author ) / Moon, J.T. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2001-01-01
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Size:295862 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Manufacturing in the 21st century-new concept for 300 mm fabKoike, A. et al. | 2001
- 1
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Manufacturing in 21^s^t Century-New Concept for 300mm Fab (Invited)Koike, A. et al. | 2001
- 5
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Design technology for systems on a chipCamposano, R. et al. | 2001
- 7
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Highly manufacturable and high performance SDR/DDR 4 Gb DRAMKim, K.N. / Jeong, H.S. / Yang, W.S. / Hwang, Y.S. / Cho, C.H. / Jeong, M.M. / Park, S. / Ahn, S.J. / Chun, Y.S. / Shin, S.H. et al. | 2001
- 9
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Scaling towards 35 nm gate length CMOSBin Yu, / Haihong Wang, / Qi Xiang, / An, J.X. / Joong Jeon, / Ming-Ren Lin, et al. | 2001
- 11
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A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIsMiyashita, K. / Nakayama, T. / Oishi, A. / Hasumi, R. / Owada, M. / Aota, S. / Okayama, Y. / Matsumoto, M. / Igarashi, H. / Yoshida, T. et al. | 2001
- 13
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Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic filmTada, M. / Ohtake, H. / Harada, Y. / Hiroi, M. / Saito, S. / Onodera, T. / Furutake, N. / Kawahara, J. / Tagami, M. / Kinoshita, K. et al. | 2001
- 15
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High-Quality Ultra-thin HfO~2 Gate Dielectric MOSFETs with TaN Electrode and Nitridation Surface PreparationChoi, R. / Kang, C. S. / Lee, B. H. / Onishi, K. / Nieh, R. / Gopalan, S. / Dharmarajan, E. / Lee, J. C. et al. | 2001
- 15
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High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparationRino Choi, / Chang Seok Kang, / Byoung Hun Lee, / Onishi, K. / Nieh, R. / Gopalan, S. / Dharmarajan, E. / Lee, J.C. et al. | 2001
- 17
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Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devicesGhani, T. / Mistry, K. / Packan, P. / Armstrong, M. / Thompson, S. / Tyagi, S. / Bohr, M. et al. | 2001
- 19
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Ultra-thin body PMOSFETs with selectively deposited Ge source/drainYang-Kyu Choi, / Daewon Ha, / Tsu-Jae King, / Chenming Hu, et al. | 2001
- 21
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Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technologyKilho Lee, / Jai-Hoon Sim, / Yujun Li, / Woo-Tag Kang, / Malik, R. / Rengarajan, R. / Chaloux, S. / Bernstein, J. / Kellerman, P. et al. | 2001
- 21
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Shallow n^+/p^+ junction formation using plasma immersion ion implantation for CMOS TechnologyLee, K. / Sim, J.-H. / Li, Y. / Kang, W.-T. / Malik, R. / Rengarajan, R. / Chaloux, S. / Bernstein, J. / Kellerman, P. et al. | 2001
- 23
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High performance sub-50 nm CMOS with advanced gate stackQi Xiang, / Bin Yu, / Haihong Wang, / Ming-Ren Lin, et al. | 2001
- 25
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A 0.115mum^2 8F^2 DRAM working cell with LPRD(Low_Prasitic_Resistance Device) and poly metal gate Technology for Gigabit DRAMNoh, H. / Cho, W. / Jeong, G. / Huh, M. / Ahn, J. / Kim, Y. / Jeong, S. / Lee, S. / Kim, D. / Kim, H. et al. | 2001
- 25
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A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAMHyunpil Noh, / Woncheol Cho, / Gucheol Jeong, / Min Huh, / Jaemin Ahn, / Ysung Kim, / Suock Jeong, / Seongjoon Lee, / Dongseok Kim, / Hazoong Kim, et al. | 2001
- 27
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A strategy for long data retention time of 512 Mb DRAM with 0.12 /spl mu/m design ruleUh, H.S. / Lee, J.K. / Ahn, Y.S. / Lee, S.H. / Hong, S.H. / Lee, J.W. / Koh, G.H. / Jeong, G.T. / Chung, T.Y. / Kinam Kim, et al. | 2001
- 27
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A Strategy for Long Data Retention Time of 512Mb DRAM with 0.12mum Design RuleUh, H. S. / Lee, J. K. / Lee, S. H. / Ahn, Y. S. / Lee, H. O. / Hong, S. H. / Lee, J. W. / Koh, G. H. / Jeong, G. T. / Chung, T. Y. et al. | 2001
- 29
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A 0.15mum Logic based embedded DRAM technology featuring 0.425mum^2 Stacked Cell using MIM (Metal-Insulator-Metal) CapacitorTakeuchi, M. / Inoue, K. / Sakao, M. / Sakoh, T. / Kitamura, T. / Arai, S. / Iizuka, T. / Yamamoto, T. / Shirai, H. / Aoki, Y. et al. | 2001
- 29
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A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitorTakeuchi, M. / Inoue, K. / Sakao, M. / Sakoh, T. / Kitamura, T. / Arai, S. / Iizuka, T. / Yamamoto, T. / Shirai, H. / Aoki, Y. et al. | 2001
- 31
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W/WN/poly gate implementation for sub-130 nm vertical cell DRAMMalik, R. / Clevenger, L. / McStay, I. / Gluschenkov, O. / Robl, W. / Shafer, P. / Stojakovic, G. / Yan, W. / Naeem, M. / Ramachandran, R. et al. | 2001
- 33
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A manufacturable 25 nm planar MOSFET technologyPonomarev, Y.V. / Loo, J.J.G.P. / Dachs, C.J.J. / Cubaynes, F.N. / Verheijen, M.A. / Kaiser, M. / Van Berkum, J.G.M. / Kubicek, S. / Bolk, J. / Rovers, M. et al. | 2001
- 35
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Experimental and simulation study on sub-50 nm CMOS designPidin, S. / Shido, H. / Yamamoto, T. / Horiguchi, N. / Kurata, H. / Sugii, T. et al. | 2001
- 37
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High-performance 157 nm resist based on fluorine-containing polymerKishimura, S. / Endo, M. / Sasago, M. et al. | 2001
- 39
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Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMsNakamura, Y. / Asano, I. / Hiratani, M. / Saito, T. / Goto, H. et al. | 2001
- 39
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Oxidation-Resistant Amorphous TaN Barrier for MIM-Ta~2O~5 Capacitors in Giga-Bit DRAMsNakamura, Y. / Asano, I. / Hiratani, M. / Saito, T. / Goto, H. et al. | 2001
- 41
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A heteroepitaxial MIM-Ta/sub 2/O/sub 5/ capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyondHiratani, M. / Hamada, T. / Iijima, S. / Ohji, Y. / Asano, I. / Nakanishi, N. / Kimura, S. et al. | 2001
- 41
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A Heteroepitaxial MIM-Ta~2O~5 Capacitor with Enhanced Dielectric Constant for DRAMs of G-bit Generation and beyondHiratani, M. / Hamada, T. / Iijima, S. / Ohji, Y. / Asano, I. / Nakanishi, N. / Kimura, S. et al. | 2001
- 43
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Cylindrical Ru/SrTiO~3/Ru Capacitor Technology for 0.11mum Generation DRAMsChu, C. M. / Kiyotoshi, M. / Niwa, S. / Nakahira, J. / Eguchi, K. / Yamazaki, S. / Tsunoda, K. / Fukuda, M. / Suzuki, T. / Nakabayashi, M. et al. | 2001
- 43
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Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMsChu, C.M. / Kiyotoshi, M. / Niwa, S. / Nakahira, J. / Eguchi, K. / Yamazaki, S. / Tsunoda, K. / Fukuda, M. / Suzuki, T. / Nakabayashi, M. et al. | 2001
- 45
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Metal gate work function adjustment for future CMOS technologyQiang Lu, / Lin, R. / Ranade, P. / Tsu-Jae King, / Chenming Hu, et al. | 2001
- 47
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Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devicesYou-Seok Suh, / Heuss, G. / Huicai Zhong, / Shin-Nam Hong, / Misra, V. et al. | 2001
- 47
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Electrical Characteristics of TaSi~xN~y Gate Electrodes For Dual Gate Si-CMOS DevicesSuh, Y.-S. / Heuss, G. / Zhong, H. / Hong, S.-N. / Misra, V. et al. | 2001
- 49
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Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gatesYee-Chia Yeo, / Ranade, P. / Qiang Lu, / Lin, R. / Tsu-Jae King, / Chenming Hu, et al. | 2001
- 49
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Effects of High-k Dielectrics on the Workfunctions of Metal and Silicon GatesYeo, Y.-C. / Ranade, P. / Lu, Q. / Lin, R. / King, T.-J. / Hu, C. et al. | 2001
- 51
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Electron wavefunction penetration into gate dielectric and interface scattering-an alternative to surface roughness scattering modelPolishchuk, I. / Chenming Hu, et al. | 2001
- 53
-
Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effectsQiqing Ouyang, / Xiangdong Chen, / Tasch, A.F. / Register, L.F. / Banerjee, S.K. / Chu, J.O. / Ott, J.A. et al. | 2001
- 55
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High performance 40 nm vertical MOSFET within a conventional CMOS process flowJosse, E. / Skotnicki, T. / Jurczak, M. / Paoli, M. / Tormen, B. / Dufartre, D. / Ribot, P. / Villaret, A. / Sondergard, E. et al. | 2001
- 57
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Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bondingHuang, L.-J. / Chu, J.O. / Goma, S. / D'Emic, C.P. / Koester, S.J. / Canaperi, D.F. / Mooney, P.M. / Cordes, S.A. / Speidell, J.L. / Anderson, R.M. et al. | 2001
- 59
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Strained Si NMOSFETs for high performance CMOS technologyRim, K. / Koester, S. / Hargrove, M. / Chu, J. / Mooney, P.M. / Ott, J. / Kanarsky, T. / Ronsheim, P. / Ieong, M. / Grill, A. et al. | 2001
- 61
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Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETsRhee, H.S. / Bae, G.J. / Choe, T.H. / Kim, S.S. / Song, S. / Lee, N.I. / Fujihara, K. / Kang, H.K. / Moon, J.T. et al. | 2001
- 63
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Performance improvement of metal gate CMOS technologiesMatsuda, S. / Yamakawa, H. / Azuma, A. / Toyoshima, Y. et al. | 2001
- 65
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Novel damage-free direct metal gate process using atomic layer depositionDae-Gyu Park, / Kwan-Yong Lim, / Heung-Jae Cho, / Tae-Ho Cha, / Joong-Jung Kim, / Jung-Kyu Ko, / Ins-Seok Yeo, / Jin Won Park, et al. | 2001
- 67
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Low Resistivity bcc-Ta/TaNx Metal Gate MNSFETs Having Plane Gate Structure Featuring Fully Low-Temperature Processing below 450^oCShimada, H. / Ohshima, I. / Nakao, S. / Nakagawa, M. / Kanemoto, K. / Hirayama, M. / Sugawa, S. / Ohmi, T. et al. | 2001
- 67
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Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/CShimada, H. / Ohshima, I. / Nakao, S.-I. / Nakagawa, M. / Kanemoto, K. / Hirayama, M. / Sugawa, S. / Ohmi, T. et al. | 2001
- 69
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50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantationCheolmin Park, / Seong-Dong Kim, / Yun Wang, / Talwar, S. / Woo, J.C.S. et al. | 2001
- 71
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High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectricMaszara, W.P. / Krishnan, S. / Xiang, Q. / Lin, M.-R. et al. | 2001
- 73
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Impact of CMOS process scaling and SOI on the soft error rates of logic processesHareland, S. / Maiz, J. / Alavi, M. / Mistry, K. / Walsta, S. / Changhong Dai, et al. | 2001
- 75
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Effects of gate-to-body tunneling current on PD/SOI CMOS SRAMJoshi, R.V. / Chuang, C.T. / Fung, S.K.H. / Assaderaghi, F. / Sherony, M. / Yang, I. / Shahidi, G. et al. | 2001
- 77
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Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxideMomose, H.S. / Ohguro, T. / Nakamura, S. / Toyoshima, Y. / Ishiuchi, H. / Iwai, H. et al. | 2001
- 77
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Study of water orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxideMomose, H. S. / Ohguro, T. / Nakamura, S. / Toyoshima, Y. / Ishiuchi, H. / Iwai, H. et al. | 2001
- 79
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A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chipOno, A. / Fukasaku, K. / Hirai, T. / Makabe, M. / Koyama, S. / Ikezawa, N. / Ando, K. / Suzuki, T. / Imai, K. / Nakamura, N. et al. | 2001
- 81
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Controlling Base-SiO~2 Density of Low-Leakage 1.6nm Gate-SiON for High-Performance and Highly Reliable n/pFETsTogo, M. / Watanabe, K. / Terai, M. / Kimura, S. / Morioka, A. / Yamamoto, T. / Tatsumi, T. / Mogami, T. et al. | 2001
- 81
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Controlling base-SiO/sub 2/ density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETsTogo, M. / Watanabe, K. / Terai, M. / Kimura, S. / Morioka, A. / Yamamoto, T. / Tatsumi, T. / Mogami, T. et al. | 2001
- 83
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Radical nitridation in multi-oxide process for 100 nm generation CMOS technologyYasuda, Y. / Kimizuka, N. / Watanabe, K. / Tatsumi, T. / Ono, A. / Fukasaku, K. / Imai, K. / Nakamura, N. et al. | 2001
- 85
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A 0.13-mum SOI CMOS Technology for Low-power Digital and RF ApplicationsZamdmer, N. / Ray, A. / Plouchart, J.-O. / Wagner, L. / Fong, N. / Jenkins, K. A. / Jin, W. / Smeys, P. / Yang, I. / Shahidi, G. et al. | 2001
- 85
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A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applicationsZamdmer, N. / Ray, A. / Plouchart, J.-O. / Wagner, L. / Fong, N. / Jenkins, K.A. / Jin, W. / Smeys, P. / Yang, I. / Shahidi, G. et al. | 2001
- 87
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Deep sub-micron CMOS device design for low power analog applicationsDeshpande, H.V. / Cheng, B. / Woo, J.C.S. et al. | 2001
- 89
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Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applicationsChun-Yen Chang, / Jiong-Guang Su, / Heng-Ming Hsu, / Shyh-Chyi Wong, / Tiao-Yuan Huang, / Yuan-Chen Sun, et al. | 2001
- 89
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Investigations of Bulk Dynamic Threshold-Voltage MOSFET with 65GHz "Normal-Mode" Ft and 220GHz "Over-Drive Mode" Ft for RF ApplicationsChang, C.-Y. / Su, J.-G. / Hsu, H.-M. / Wong, S.-C. / Huang, T.-Y. / Sun, Y.-C. et al. | 2001
- 91
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A study of analog characteristics of CMOS with heavily nitrided NO oxynitridesOhguro, T. / Nagano, T. / Fujiwara, M. / Takayanagi, M. / Shimizu, T. / Momose, H.S. / Nakamura, S. / Toyoshima, Y. et al. | 2001
- 93
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Transistor-limited constant voltage stress of gate dielectricsLinder, B.P. / Frank, D.J. / Stathis, J.H. / Cohen, S.A. et al. | 2001
- 95
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Statistical analysis of soft breakdown in ultrathin gate oxidesMizubayashi, W. / Yoshida, Y. / Miyazaki, S. / Hirose, M. et al. | 2001
- 97
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A new quantitative hydrogen-based model for ultra-thin oxide breakdownSune, J. / Wu, E. et al. | 2001
- 99
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Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regimeTakayanagi, M. / Takagi, S. / Toyoshima, Y. et al. | 2001
- 101
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A 0.13mum CMOS Platform with Cu/Low-k Interconnects for System On Chip ApplicationsSchiml, T. / Biesemans, S. / Brase, G. / Burrell, L. / Cowley, A. / Chen, K. C. / Ehrenwall, A. v. / Ehrenwall, B. v. / Felsner, P. / Gill, J. et al. | 2001
- 101
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A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applicationsSchiml, T. / Biesemans, S. / Brase, G. / Burrell, L. / Cowley, A. / Chen, K.C. / Von Ehrenwall, A. / Von Ehrenwall, B. / Felsner, P. / Gill, J. et al. | 2001
- 103
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A High Performance 0.12mum CMOS with Manufacturable 0.18mum TechnologyIchinose, K. / Saito, T. / Yanagida, Y. / Nonaka, Y. / Torii, K. / Sato, H. / Saito, N. / Wada, S. / Mori, K. / Mitani, S. et al. | 2001
- 103
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A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technologyIchinose, K. / Saito, T. / Yanagida, Y. / Nonaka, Y. / Torii, K. / Sato, H. / Saito, N. / Wada, S. / Mori, K. / Mitani, S. et al. | 2001
- 105
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High-density and high-performance 6T-SRAM for system-on-chip in 130 nm CMOS technologyKong, W. / Venkatraman, R. / Castagnetti, R. / Duan, F. / Ramesh, S. et al. | 2001
- 107
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Scalability and biasing strategy for CMOS with active well biasShih-Fen Huang, / Wann, C. / Yu-Shyang Huang, / Chih-Yung Lin, / Schafbauer, T. / Shui-Ming Cheng, / Yao-Ching Cheng, / Vietzke, D. / Eller, M. / Chuan Lin, et al. | 2001
- 109
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High-K Gate Dielectrics: Is It Necessary? If So, When, What, How?Niwa, M. / Lee, J. C. et al. | 2001
- 109
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Which Features of an IC Technology will Benefit Radio SOC?Iwai, H. / Shichijo, S. / Hotta, M. / Abidi, A. et al. | 2001
- 110
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Extending Copper/low k Interconnects to 100nm and Beyond: How "Low" Can We Go? Are There Any Alternative Approaches?Hayashi, Y. / Havemann, B. et al. | 2001
- 110
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Technology Challenges and Solutions for Scaling Flash Memory-What Do the Next Ten Years Promise?Shirota, R. / Parat, K. et al. | 2001
- 111
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Highly Scalable sub-10F^2 1T1C COB Cell for high density FRAMLee, S. Y. / Kim, H. H. / Jung, D. J. / Song, Y. J. / Jang, N. W. / Choi, M. K. / Jeon, B. K. / Lee, Y. T. / Lee, K. M. / Joo, S. H. et al. | 2001
- 111
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Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAMLee, S.Y. / Kim, H.H. / Jung, D.J. / Song, Y.J. / Jang, N.W. / Choi, M.K. / Jeon, B.K. / Lee, Y.T. / Lee, K.M. / Joo, S.H. et al. | 2001
- 113
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A fully planarized 8M bit ferroelectric RAM with 'chain' cell structureOzaki, T. / Iba, J. / Kanaya, H. / Morimoto, T. / Hidaka, O. / Taniguchi, A. / Kumura, Y. / Yamakawa, K. / Oowaki, Y. / Kunishima, I. et al. | 2001
- 113
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A Fully Planalized 8M bit Ferroelectric RAM with `Chain' Cell StructureOzaki, T. / Iba, J. / Yamada, Y. / Kanaya, H. / Morimoto, T. / Hidaka, O. / Taniguchi, A. / Kumura, Y. / Yamakawa, K. / Oowaki, Y. et al. | 2001
- 115
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A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memoryYamada, R. / Sekiguchi, T. / Okuyama, Y. / Yugami, J. / Kume, H. et al. | 2001
- 117
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New considerations for highly reliable PMOSFETs in 100 nm generation and beyondMorifuji, E. / Kumamori, T. / Muta, M. / Suzuki, K. / De, I. / Shibkov, A. / Saxena, S. / Enda, T. / Aoki, N. / Asano, W. et al. | 2001
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Impact of low-standby-power device design on hot carrier reliabilityMurakami, E. / Umeda, K. / Yamanaka, T. / Kimura, S. / Aono, H. / Makabe, K. / Okuyama, K. / Ohji, Y. / Yoshida, Y. / Minami, M. et al. | 2001
- 121
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Consistent model for short-channel nMOSFET post-hard-breakdown characteristicsKaczer, B. / Degraeve, R. / De Keersgieter, A. / Van de Mieroop, K. / Bearda, T. / Groeseneken, G. et al. | 2001
- 123
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Realization of high performance dual gate DRAMs without boron penetration by application of tetrachlorosilane silicon nitride filmsTanaka, M. / Saida, S. / Inoue, F. / Kojima, M. / Nakanishi, T. / Suguro, K. / Tsunashima, Y. et al. | 2001
- 125
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Retention Time Improvement by Fast-Pull and Fast-Cool[FPFC] Ingot Growing Combined with Proper Arrangement of Subsequent Thermal Budget for 0.81um DRAM Cell and beyondIlgweon, K. / Jaesoon, K. / Kyosung, L. / Dongchan, K. / Jungho, S. / Junho, C. / Namsung, K. / Heesik, Y. / Youngil, C. / Juseok, P. et al. | 2001
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Retention time improvement by fast-pull and fast-cool (FPFC) ingot growing combined with proper arrangement of subsequent thermal budget for 0.18 /spl mu/m DRAM cell and beyondKim Ilgweon, / Kwon Jaesoon, / Lee Kyosung, / Kim Dongchan, / Shin Jungho, / Choy Junho, / Kim Namsung, / Yang Heesik, / Cheon Youngil, / Park Juseok, et al. | 2001
- 127
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DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plugBeom-Jun Jin, / Young-Pil Kim, / Byeong-Yun Nam, / Hyoung-Joon Kim, / Young-Wook Park, / Joo-Tae Moon, et al. | 2001
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DRAM scaling-down to 0.1mum generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plugJin, B.-J. / Kim, Y.-P. / Nam, B.-Y. / Kim, H.-J. / Park, Y.-W. / Moon, J.-T. et al. | 2001
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A New Storage Node Pad Formation Technology-Line Type SAC with Oxide Spacer(LSOS) and Direct Metal Plug(DMP)-for 0.115mum Tech and BeyondYoon, K. H. / Park, S. C. / Lee, M. S. / Huh, M. / Bae, Y. H. / Kim, S. I. / Kim, J. W. / Yoon, H. K. et al. | 2001
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A new storage node pad formation technology-line type SAC with oxide spacer (LSOS) and direct metal plug (DMP)-for 0.115 /spl mu/m tech and beyondYoon, K.H. / Park, S.C. / Lee, M.S. / Huh, M. / Bae, Y.H. / Kim, S.I. / Kim, J.W. / Yoon, H.K. et al. | 2001
- 131
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Dopant Penetration Effects on Polysilicon Gate HfO~2 MOSFET'sOnishi, K. / Kang, L. / Choi, R. / Dharmarajan, E. / Gopalan, S. / Jeon, Y. / Kang, C. S. / Lee, B. H. / Nieh, R. / Lee, J. C. et al. | 2001
- 131
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Dopant penetration effects on polysilicon gate HfO/sub 2/ MOSFET'sOnishi, K. / Kang, L. / Choi, R. / Dharmarajan, E. / Gopalan, S. / Yongjoo Jeon, / Chang Seok Kang, / Byoung Hun Lee, / Nieh, R. / Lee, J.C. et al. | 2001
- 133
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Performance and Reliability of Ultra Thin CVD HfO~2 Gate Dielectrics with Dual Poly-Si Gate ElectrodesLee, S. J. / Luan, H. F. / Lee, C. H. / Jeon, T. S. / Bai, W. P. / Senzaki, Y. / Roberts, D. / Kwong, D. L. et al. | 2001
- 133
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Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodesLee, S.J. / Luan, H.F. / Lee, C.H. / Jeon, T.S. / Bai, W.P. / Senzaki, Y. / Roberts, D. / Kwong, D.L. et al. | 2001
- 135
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Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applicationsLuo, Z.J. / Ma, T.P. / Cartier, E. / Copel, M. / Tamagawa, T. / Halpern, B. et al. | 2001
- 135
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Ultra-thin ZrO~2 (or Silicate) with High Thermal Stability for CMOS Gate ApplicationsLuo, Z. J. / Ma, T. P. / Cartier, E. / Copel, M. / Tamagawa, T. / Halpern, B. et al. | 2001
- 137
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MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodesLee, C.H. / Kim, Y.H. / Luan, H.F. / Lee, S.J. / Jeon, T.S. / Bai, W.P. / Kwong, D.L. et al. | 2001
- 137
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MOS Devices with High Quality Ultra Thin CVD ZrO~2 Gate Dielectrics and Self-Aligned TaN and TaN/Poly-Si Gate ElectrodesLee, C. H. / Kim, Y. H. / Luan, H. F. / Lee, S. J. / Jeon, T. S. / Bai, W. P. / Kwong, D. L. et al. | 2001
- 139
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Optimization of annealing conditions for dual damascene Cu microstructures and via chain yieldsQing-Tang Jiang, / Frank, A. / Havemann, R.H. / Parihar, V. / Nowell, M. et al. | 2001
- 139
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Optimizaion of Annealing Conditions for Dual Damascene Cu Microstructures and Via Chain YieldsJiang, Q.-T. / Frank, A. / Havemann, R. H. / Parihar, V. / Nowell, M. et al. | 2001
- 141
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Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnectsTing-Yen Chiang, / Saraswat, K.C. et al. | 2001
- 143
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Scaling scenario of multi-level interconnects for future CMOS LSIYoshimura, H. / Asahi, Y. / Matsuoka, F. et al. | 2001
- 145
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Non-uniform chip-temperature dependent signal integrityAjami, A.H. / Banerjee, K. / Pedram, M. et al. | 2001
- 147
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Author index| 2001
- i
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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)| 2001