Automatic Design Space Exploration of Register Bypasses in Embedded Processors (English)
- New search for: Shrivastava, A.
- New search for: Park Sanghyun,
- New search for: Earlie, E.
- New search for: Dutt, N.D.
- New search for: Nicolau, A.
- New search for: Paek Yunheung,
- New search for: Shrivastava, A.
- New search for: Park Sanghyun,
- New search for: Earlie, E.
- New search for: Dutt, N.D.
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In:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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26
, 12
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2102-2115
;
2007
- Article (Journal) / Electronic Resource
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Title:Automatic Design Space Exploration of Register Bypasses in Embedded Processors
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Contributors:Shrivastava, A. ( author ) / Park Sanghyun, ( author ) / Earlie, E. ( author ) / Dutt, N.D. ( author ) / Nicolau, A. ( author ) / Paek Yunheung, ( author )
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Published in:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; 26, 12 ; 2102-2115
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Publisher:
- New search for: IEEE
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Publication date:2007-12-01
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Size:1324187 byte
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents – Volume 26, Issue 12
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2089
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Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit AnalysisWei Dong, / Peng Li, et al. | 2007
- 2089
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Analog Design - Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit AnalysisDong, W. et al. | 2007
- 2102
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Automatic Design Space Exploration of Register Bypasses in Embedded ProcessorsShrivastava, A. / Park Sanghyun, / Earlie, E. / Dutt, N.D. / Nicolau, A. / Paek Yunheung, et al. | 2007
- 2102
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Architectural Design - Automatic Design Space Exploration of Register Bypasses in Embedded ProcessorsShrivastava, A. et al. | 2007
- 2116
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A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear SystemsBond, B.N. / Daniel, L. et al. | 2007
- 2116
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Modeling - A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear SystemsBond, B.N. et al. | 2007
- 2130
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BoxRouter: A New Global Router Based on Box Expansion and Progressive ILPMinsik Cho, / Pan, D.Z. et al. | 2007
- 2130
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Physical Design - BoxRouter: A New Global Router Based on Box Expansion and Progressive ILPCho, M. et al. | 2007
- 2144
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Detailed Placement for Enhanced Control of Resist and Etch CDsGupta, P. / Kahng, A.B. / Park Chul-Hong, et al. | 2007
- 2144
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Physical Design - Detailed Placement for Enhanced Control of Resist and Etch CDsGupta, P. et al. | 2007
- 2158
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Diffusion-Based Placement Migration With Application on LegalizationHaoxing Ren, / Pan, D.Z. / Alpert, C.J. / Villarrubia, P.G. / Gi-Joon Nam, et al. | 2007
- 2158
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Physical Design - Diffusion-Based Placement Migration With Application on LegalizationRen, H. et al. | 2007
- 2173
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Physical Design - ECO-System: Embracing the Change in PlacementRoy, J.A. et al. | 2007
- 2173
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ECO-System: Embracing the Change in PlacementRoy, J.A. / Markov, I.L. et al. | 2007
- 2186
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System Design - Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual SynchronizationYi, Y. et al. | 2007
- 2186
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Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual SynchronizationYoungmin Yi, / Dohyung Kim, / Soonhoi Ha, et al. | 2007
- 2201
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Testing Network-on-Chip Communication FabricsGrecu, C. / Ivanov, A. / Saleh, R. / Pande, P.P. et al. | 2007
- 2201
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Testing - Testing Network-on-Chip Communication FabricsGrecu, C. et al. | 2007
- 2215
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SHORT PAPERS - Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated ClocksBaeg, S. et al. | 2007
- 2215
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Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated ClocksSanghyeon Baeg, et al. | 2007
- 2222
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A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor DesignWen-Wen Hsieh, / Po-Yuan Chen, / Chun-Yao Wang, / TingTing Hwang, et al. | 2007
- 2222
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SHORT PAPERS - A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor DesignHsieh, W.-W. et al. | 2007
- 2228
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ANNOUNCEMENTS - Information for Authors| 2007
- 2228
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors| 2007
- 2229
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2007 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 26| 2007
- 2229
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2007 INDEX| 2007
- C1
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Table of contents| 2007
- C2
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information| 2007
- C3
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information| 2007