On-chip process variation-tracking through an all-digital monitoring architecture (English)
- New search for: Karimiyan Alidash, H.
- New search for: Calimera, A.
- New search for: Macii, A.
- New search for: Macii, E.
- New search for: Poncino, M.
- New search for: Karimiyan Alidash, H.
- New search for: Calimera, A.
- New search for: Macii, A.
- New search for: Macii, E.
- New search for: Poncino, M.
In:
IET Circuits, Devices & Systems
;
6
, 5
;
366-373
;
2012
- Article (Journal) / Electronic Resource
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Title:On-chip process variation-tracking through an all-digital monitoring architecture
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Contributors:Karimiyan Alidash, H. ( author ) / Calimera, A. ( author ) / Macii, A. ( author ) / Macii, E. ( author ) / Poncino, M. ( author )
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Published in:IET Circuits, Devices & Systems ; 6, 5 ; 366-373
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Publisher:
- New search for: The Institution of Engineering and Technology
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Publication date:2012-12-01
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Size:8 pages
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents – Volume 6, Issue 5
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 271
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Editorial: Thermal, power and timing modeling, design and simulationAyala, J.L. / Garci´a-Ca´mara, B. et al. | 2012
- 273
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Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distributionAghababa, H. / Khosropour, A. / Afzali-Kusha, A. / Forouzandeh, B. / Pedram, M. et al. | 2012
- 279
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Low-power processor architecture exploration for online biomedical signal analysisDogan, A.Y. / Constantin, J. / Atienza, D. / Burg, A. / Benini, L. et al. | 2012
- 287
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Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction levelMbarek, O. / Pegatoquet, A. / Auguin, M. et al. | 2012
- 297
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Worst-case temperature analysis for different resource modelsSchor, L. / Yang, H. / Bacivarov, I. / Thiele, L. et al. | 2012
- 308
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Design and management of high-performance, reliable and thermal-aware 3D networks-on-chipRahmani, A.-M. / Vaddina, K.R. / Latif, K. / Liljeberg, P. / Plosila, J. / Tenhunen, H. et al. | 2012
- 322
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Power profiling-guided floorplanner for 3D multi-processor systems-on-chipArnaldo, I. / Risco-Marti´n, J.L. / Ayala, J.L. / Hidalgo, J.I. et al. | 2012
- 330
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Iterative timing analysis based on nonlinear and interdependent flipflop modellingChen, N. / Li, B. / Schlichtmann, U. et al. | 2012
- 338
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Integrator clamping for asynchronous sigma-delta modulator central frequency incrementMatic´, T. / Sˇvedek, T. / Vinko, D. et al. | 2012
- 347
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Secure D flip-flop against side channel attacksVaquie, B. / Tiran, S. / Maurine, P. et al. | 2012
- 355
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Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtimeKhan, O. / Kundu, S. et al. | 2012
- 366
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On-chip process variation-tracking through an all-digital monitoring architectureKarimiyan Alidash, H. / Calimera, A. / Macii, A. / Macii, E. / Poncino, M. et al. | 2012