8-bit serialised architecture of SEED block cipher for constrained devices (English)
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- New search for: Pirpilidis, Filippos
- New search for: Pyrgas, Lampros
- New search for: Kitsos, Paris
- New search for: Pirpilidis, Filippos
- New search for: Pyrgas, Lampros
- New search for: Kitsos, Paris
In:
IET Circuits, Devices & Systems
;
14
, 3
;
316-321
;
2020
- Article (Journal) / Electronic Resource
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Title:8-bit serialised architecture of SEED block cipher for constrained devices
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Contributors:
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Published in:IET Circuits, Devices & Systems ; 14, 3 ; 316-321
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Publisher:
- New search for: The Institution of Engineering and Technology
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Publication date:2020-02-17
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Size:6 pages
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Keywords:frequency 125.0 MHz , encryption , SEED block cipher , decryption , key generation process , S-boxes , constrained devices , BASYS3 board , 1-bit registers , FPGA slices , area constraints devices , hardware resources , field programmable gate arrays , security , cryptography , 8-bit datapath , 8-bit serialised architecture , clock cycles , composite field arithmetic
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Source:
Metadata by IET is licensed under CC BY 3.0
Table of contents – Volume 14, Issue 3
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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8-bit serialised architecture of SEED block cipher for constrained devicesPirpilidis, Filippos / Pyrgas, Lampros / Kitsos, Paris et al. | 2020
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