MetaWire: using FPGA configuration circuitry to emulate a network-on-chip (English)
- New search for: Shelburne, M.
- New search for: Patterson, C.
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- New search for: Jones, M.
- New search for: Martin, B.
- New search for: Fong, R.
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In:
IET Computers & Digital Techniques
;
4
, 3
;
159-169
;
2010
- Article (Journal) / Electronic Resource
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Title:MetaWire: using FPGA configuration circuitry to emulate a network-on-chip
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Contributors:Shelburne, M. ( author ) / Patterson, C. ( author ) / Athanas, P. ( author ) / Jones, M. ( author ) / Martin, B. ( author ) / Fong, R. ( author )
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Published in:IET Computers & Digital Techniques ; 4, 3 ; 159-169
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Publisher:
- New search for: The Institution of Engineering and Technology
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Publication date:2010-05-01
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Size:11 pages
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents – Volume 4, Issue 3
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 157
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Editorial: Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008)Kebschull, U. / Platzner, M. / Teich, J. et al. | 2010
- 157
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Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]Kebschull, U. / Platzner, M. / Teich, J. et al. | 2010
- 159
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MetaWire: using FPGA configuration circuitry to emulate a network-on-chipShelburne, M. / Patterson, C. / Athanas, P. / Jones, M. / Martin, B. / Fong, R. et al. | 2010
- 170
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Power minimisation during field programmable gate array placementVorwerk, K. / Kennings, A. / Pevzner, V. / Kundu, A. / Raman, M. / Dunoyer, J. / Hsu, Y.-C. et al. | 2010
- 184
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FPGA acceleration of rigid-molecule docking codesSukhwani, B. / Herbordt, M.C. et al. | 2010
- 196
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Fault tolerance and reliability in field-programmable gate arraysStott, E. / Sedcole, P. / Cheung, P. et al. | 2010
- 211
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Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memoriesGuillemenet, Y. / Torres, L. / Sassatelli, G. et al. | 2010
- 227
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Manipulation and optimisation techniques for Boolean logicAl Jassani, B.A. / Urquhart, N. / Almaini, A.E.A. et al. | 2010
- 240
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Fault-tolerance techniques for hybrid CMOS/nanoarchitectureMelouki, A. / Srivastava, S. / Al-Hashimi, B.M. et al. | 2010
- 251
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Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnectsFu, B. / Ampadu, P. et al. | 2010