Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation (English)
- New search for: Lee, H.-Y.
- New search for: Lee, H.-Y.
In:
IET Circuits, Devices & Systems
;
5
, 5
;
411-417
;
2011
- Article (Journal) / Electronic Resource
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Title:Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation
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Contributors:Lee, H.-Y. ( author )
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Published in:IET Circuits, Devices & Systems ; 5, 5 ; 411-417
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Publisher:
- New search for: The Institution of Engineering and Technology
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Publication date:2011-12-01
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Size:7 pages
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Keywords:
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Source:
Table of contents – Volume 5, Issue 5
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASICMali´k, P. et al. | 2011
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M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parametersShedabale, S. / Russell, G. / Yakovlev, A. et al. | 2011
- 411
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Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensationLee, H.-Y. et al. | 2011
- 418
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Output-capacitorless low-dropout regulator using a cascoded flipped voltage followerBlakiewicz, G. et al. | 2011
- 424
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