A Cost-Effective Design For Testability: Clock Line Control and Test Generation Using Selective Clocking (English)
- New search for: Baeg, S.
- New search for: Baeg, S.
- New search for: Rogers, W.A.
In:
IEEE transactions on computer-aided design of integrated circuits and systems
;
18
, 6
; 850-860
;
1999
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ISSN:
- Article (Journal) / Print
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Title:A Cost-Effective Design For Testability: Clock Line Control and Test Generation Using Selective Clocking
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Contributors:Baeg, S. ( author ) / Rogers, W.A.
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Published in:
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:1999
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 770/3155/5670
- New search for: 53.52 / 33.72 / 33.61 / 53.51
- Further information on Basic classification
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Keywords:
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Classification:
Local classification TIB: 770/3155/5670 BKL: 53.52 Elektronische Schaltungen / 33.72 Halbleiterphysik / 33.61 Festkörperphysik / 53.51 Bauelemente der Elektronik -
Source:
Table of contents – Volume 18, Issue 6
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 669
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Primitive Delay Faults: Identification, Testing and Design for TestabilityKrstic, A. et al. | 1999
- 685
-
Combining Multiple DFT Schemes with Test GenerationMathew, B. et al. | 1999
- 697
-
High-Level Area and Power Estimation for VLSI CircuitsNemani, M. et al. | 1999
- 714
-
Models and Algorithms for Bounds on Leakage in CMOS CircuitsJohnson, M.C. et al. | 1999
- 726
-
A Minimum-Cost Cirulation Approach to DSP Address-Code GenerationGebotys, C.H. et al. | 1999
- 726
-
A Minimum-Cost Circulation Approach to DSP Address-Code GenerationGebotys, C. H. et al. | 1999
- 742
-
Hierarchical Finite State Machines with Multiple Concurrency ModelsGirault, A. / Lee, B. / Lee, E. A. et al. | 1999
- 742
-
Hierachical Finite State Machines with Multiple Concurrency ModelsGirault, A. et al. | 1999
- 761
-
An Output Encoding Problem and a Solution TechniqueMitra, S. et al. | 1999
- 769
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POSET timing and its application to the synthesis and verification of gate-level timed circuitsMyers, C.J. / Rokicki, T.G. / Meng, T.H.Y. et al. | 1999
- 769
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POSET Timing and Its Application to the Synthesis and Verifcation of Gate-Level Timed CircuitsMyers, C. J. / Rokicki, T. G. / Meng, T. H.-Y. et al. | 1999
- 769
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POSET Timing and Its Application th the Synthesis and Verification of Gate-Level Timed CircuitsMyers, C.J. et al. | 1999
- 787
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A Quadratic Programming Approach to Simultaneous Buffer Insertion-Sizing and Wire SizingChu, C.C.N. et al. | 1999
- 799
-
Delay Optimal Clustering Targeting Low-Power VLSI CircuitsVaishnav, H. et al. | 1999
- 813
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Policy Optimization for Dynamic Power ManagementBenini, L. et al. | 1999
- 834
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Synthesis of Software Programs for Embedded Control ApplicationsBalarin, F. et al. | 1999
- 850
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A Cost-Effective Design For Testability: Clock Line Control and Test Generation Using Selective ClockingBaeg, S. et al. | 1999
- 861
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Using Configurable Computing to Accelerate Boolean SatisfiabilityZhong, P. et al. | 1999