MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip (English)
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In:
IEEE transactions on very large scale integration (VLSI) systems
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16
, 8
; 1046-1057
;
2008
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ISSN:
- Article (Journal) / Print
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Title:MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 16, 8 ; 1046-1057
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2008
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 16, Issue 8
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 941
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Power-Energy Analysis and Optimization - Satisfiability Models for Maximum Transition PowerRoy, S. et al. | 2008
- 941
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Satisfiability Models for Maximum Transition PowerRoy, S. / Chakrabarti, P.P. / Dasgupta, P. et al. | 2008
- 952
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Energy-Aware Flash Memory Management in Virtual Memory SystemHan-Lin Li, / Chia-Lin Yang, / Hung-Wei Tseng, et al. | 2008
- 965
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Hybrid-Type CAM Design for Both Power and Performance EfficiencyYen-Jen Chang, / Yuan-Hong Liao, et al. | 2008
- 975
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A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate SizingMahalingam, V. / Ranganathan, N. / Harlow, J.E. et al. | 2008
- 985
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Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active IntervalsRakhmatov, Daler et al. | 2008
- 999
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Cost-Efficient SHA Hardware AcceleratorsChaves, R. / Kuzmanov, G. / Sousa, L. / Vassiliadis, S. et al. | 2008
- 999
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Architecture-System Level Performance Optimization - Cost-Efficient SHA Hardware AcceleratorsChaves, R. et al. | 2008
- 1009
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Improving Error Tolerance for Multithreaded Register FilesLei Wang, / Patel, N. et al. | 2008
- 1021
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TDM Virtual-Circuit Configuration for Network-on-ChipZhonghai Lu, / Jantsch, A. et al. | 2008
- 1035
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Testing and DFT - Automatic Test Generation for Combinational Threshold Logic NetworksGupta, P. et al. | 2008
- 1035
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Automatic Test Generation for Combinational Threshold Logic NetworksGupta, P. / Zhang, R. / Jha, N.K. et al. | 2008
- 1046
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MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-ChipDan Zhao, / Yi Wang, et al. | 2008
- 1058
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Reconfigurable Circuits - Cost-Effective Triple-Mode Reconfigurable Pipeline FFT-IFFT-2-D DCT ProcessorLin, C.-T. et al. | 2008
- 1058
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Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT ProcessorChin-Teng Lin, / Yuan-Chu Yu, / Lan-Da Van, et al. | 2008
- 1072
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Configurable VLSI Architecture for Deblocking Filter in H.264/AVCChung-Ming Chen, / Chung-Ho Chen, et al. | 2008
- 1083
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Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGANoseworthy, J. / Leeser, M. et al. | 2008
- 1083
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FPGA - Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGANoseworthy, J. et al. | 2008
- 1091
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Transition Skew Coding for Global On-Chip InterconnectAkl, C.J. / Bayoumi, M.A. et al. | 2008
- 1091
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TRANSACTIONS BRIEFS - Transition Skew Coding for Global On-Chip InterconnectAkl, C.J. et al. | 2008
- 1096
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Effective Uses of FPGAs for Brute-Force Attack on RC4 CiphersKwok, S. / Lam, E.Y. et al. | 2008
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Table of contents| 2008
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2008
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2008
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2008