Article 2 (24 pages) - CoMPSoC: A Template for Composable and Predictable Multi-Processor System on Chips (English)
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ACM transactions on design automation of electronic systems
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14
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2009
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Title:Article 2 (24 pages) - CoMPSoC: A Template for Composable and Predictable Multi-Processor System on Chips
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Place of publication:New York, NY
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Publication date:2009
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 14, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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SystemCoDesigner-An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming ApplicationsKeinert, J. / Streubuhr, M. / Schlichter, T. / Falk, J. / Gladigau, J. / Haubelt, C. / Teich, J. / Meredith, M. et al. | 2009
- 2
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CoMPSoC:A Template for Composable and Predictable Multi-Processor System on ChipsHansson, A. / Goossens, K. / Bekooij, M. / Huisken, J. et al. | 2009
- 3
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System Scenario-based Design of Dynamic Embedded SystemsGheorghita, S.V. / Palkovic, M. / Hamers, J. / Vandecappelle, A. / Mamagkakis, S. / Basten, T. / Eeckhout, L. / Corporaal, H. / Catthoor, F. / Vandeputte, F. et al. | 2009
- 4
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SOC Test-Architecture Optimization for the Testing of Embedded Cores and Signal-Integrity Faults on Core-External InterconnectsXu, Q. / Zhang, Y. / Chakrabarty, K. et al. | 2009
- 5
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A Gateway Node with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor NetworksJin, Z. / Schurgers, C. / Gupta, R.K. et al. | 2009
- 6
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An Energy-Efficient I/O Request Mechanism for Multi-Bank Flash-Memory Storage SystemsWu, C.-H. et al. | 2009
- 7
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A Design Automation and Power Estimation Flow for RFID SystemsDontharaju, S. / Tung, S. / Cain, J.T. / Mats, L. / Mickle, M.H. / Jones, A.K. et al. | 2009
- 8
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Provably Efficient Algorithms for Resolving Temporal and Spatial Difference Constraint ViolationsDasdan, A. et al. | 2009
- 9
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Design Intent Coverage RevisitedSinha, A. / Dasgupta, P. / Pal, B. / Das, S. / Basu, P. / Chakrabarti, P.P. et al. | 2009
- 10
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Model Checking Sequential Software Programs Via Mixed Symbolic AnalysisYang, Z. / Wang, H. / Gupta, A. / Ivancic, F. et al. | 2009
- 11
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Interconnect Customization for a Hardware FabricMehta, G. / Stander, J. / Baz, M. / Hunsaker, B. / Jones, A.K. et al. | 2009
- 12
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Congestion Prediction in Early Stages of Physical DesignSham, C.-W. / Young, E.F.Y. / Lu, J. et al. | 2009
- 13
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Energy and Switch Area Optimizations for FPGA Global Routing ArchitecturesZhu, Y. / Hu, Y. / Taylor, M.B. / Cheng, C.-K. et al. | 2009
- 14
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Opposite-Phase Register Switching for Peak Current MinimizationHuang, S.-H. / Chang, C.-M. / Nieh, Y.-T. et al. | 2009
- 15
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Straightforward Construction of Depth-Size Optimal, Parallel Prefix Circuits with Fan-Out 2Lin, Y.-C. / Hung, L.-L. et al. | 2009
- 16
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Lens Aberration Aware Placement for Timing YieldKahng, A.B. / Park, C.-H. / Sharma, P. / Wang, Q. et al. | 2009
- 17
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A 252Kgates/4.9Kbytes SRAM/71 mW Multistandard Video Decoder for High Definition Video ApplicationsChien, C.-D. / Chien, C.-A. / Chu, J.-C. / Guo, J.-I. / Cheng, C.-H. et al. | 2009
- 18
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Efficient Error Detection Codes for Multiple-Bit Upset Correction in SRAMs with BICSReviriego, P. / Maestro, J.A. et al. | 2009
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Article 6 (25 pages) - An Energy-Efficient I-O Request Mechanism for Multi-Bank Flash-Memory Storage SystemsWu, C.-H. et al. | 2009
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Article 11 (32 pages) - Interconnect Customization for a Hardware FabricMehta, G. et al. | 2009
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Article 10 (26 pages) - Model Checking Sequential Software Programs Via Mixed Symbolic AnalysisYang, Z. et al. | 2009
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Article 9 (32 pages) - Design Intent Coverage RevisitedSinha, A. et al. | 2009
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Article 15 (13 pages) - Straightforward Construction of Depth-Size Optimal, Parallel Prefix Circuits with Fan-Out 2Lin, Y.-C. et al. | 2009
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Article 3 (45 pages) - System Scenario-based Design of Dynamic Embedded SystemsGheorghita, S.V. et al. | 2009
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Article 12 (18 pages) - Congestion Prediction in Early Stages of Physical DesignSham, C.-W. et al. | 2009
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Article 1 (23 pages) - SYSTEMCODESIGNER — An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming ApplicationsKeinert, J. et al. | 2009
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Article 4 (27 pages) - SOC Test-Architecture Optimization for the Testing of Embedded Cores and Signal-Integrity Faults on Core-External InterconnectsXu, Q. et al. | 2009
-
Article 14 (29 pages) - Opposite-Phase Register Switching for Peak Current MinimizationHuang, S.-H. et al. | 2009
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Article 13 (25 pages) - Energy and Switch Area Optimizations for FPGA Global Routing ArchitecturesZhu, Y. et al. | 2009
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Article 2 (24 pages) - CoMPSoC: A Template for Composable and Predictable Multi-Processor System on ChipsHansson, A. et al. | 2009
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Article 7 (31 pages) - A Design Automation and Power Estimation Flow for RFID SystemsDontharaju, S. et al. | 2009
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Article 18 (10 pages) - Efficient Error Detection Codes for Multiple-Bit Upset Correction in SRAMs with BICSReviriego, P. et al. | 2009
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Article 5 (17 pages) - A Gateway Node with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor NetworksJin, Z. et al. | 2009
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Article 17 (17 pages) - A 252Kgates-4.9Kbytes SRAM-71 mW Multistandard Video Decoder for High Definition Video ApplicationsChien, C.-D. et al. | 2009
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Article 8 (22 pages) - Provably Efficient Algorithms for Resolving Temporal and Spatial Difference Constraint ViolationsDasdan, A. et al. | 2009
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Article 16 (26 pages) - Lens Aberration Aware Placement for Timing YieldKahng, A.B. et al. | 2009