Clocking - Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees (English)
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IEEE transactions on very large scale integration (VLSI) systems
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20
, 1
; 66-80
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2012
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ISSN:
- Article (Journal) / Print
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Title:Clocking - Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 20, 1 ; 66-80
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2012
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 20, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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A MITE-Based Translinear FPAASchlottmann, C. R. / Abramson, D. / Hasler, P. E. et al. | 2012
- 1
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Analog Circuits - A MITE-Based Translinear FPAASchlottmann, C R et al. | 2012
- 10
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A High-Level Simulink-Based Tool for FPAA ConfigurationSchlottmann, C. R. / Petre, C. / Hasler, P. E. et al. | 2012
- 19
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Memories - Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 CacheSun, H et al. | 2012
- 19
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Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 CacheHongbin Sun, / Chuanyin Liu, / Wei Xu, / Jizhong Zhao, / Nanning Zheng, / Tong Zhang, et al. | 2012
- 29
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Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention FailuresNourivand, A. / Al-Khalili, Asim J. / Savaria, Y. et al. | 2012
- 42
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Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS CircuitsMeijer, M. / de Gyvez, J. P. et al. | 2012
- 42
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VLSI Design - Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS CircuitsMeijer, M et al. | 2012
- 52
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FISH: Fast Instruction SyntHesis for Custom ProcessorsAtasu, K. / Luk, W. / Mencer, O. / Ozturan, C. / Dundar, G. et al. | 2012
- 66
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Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock TreesJinwook Jang, / Franza, O. / Burleson, W. et al. | 2012
- 66
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Clocking - Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock TreesJang, J et al. | 2012
- 80
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A 104-GHz Phase-Locked Loop Using a VCO at Second Pole FrequencyKun-Hung Tsai, / Shen-Iuan Liu, et al. | 2012
- 89
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Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential LinkWei Yao, / Yiyu Shi, / Lei He, / Pamarti, S. et al. | 2012
- 98
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Reliability Modeling and Management of Nanophotonic On-Chip NetworksZheng Li, / Mohamed, M. / Xi Chen, / Dudley, E. / Ke Meng, / Li Shang, / Mickelson, A. R. / Joseph, R. / Vachharajani, M. / Schwartz, B. et al. | 2012
- 98
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Network On-Chip - Reliability Modeling and Management of Nanophotonic On-Chip NetworksLi, Z et al. | 2012
- 112
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Hardware Security - A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation TimeSalmani, H et al. | 2012
- 112
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A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation TimeSalmani, H. / Tehranipoor, M. / Plusquellic, J. et al. | 2012
- 126
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A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded CoresGeng-Ming Chiu, / Li, James Chien-Mo et al. | 2012
- 135
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Communications Circuits - A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 μm CMOSShabany, M et al. | 2012
- 135
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A 675 Mbps, 4 Formula Not Shown 4 64-QAM K-Best MIMO Detector in 0.13 Formula Not Shown CMOSShabany, M. / Gulak, P. G. et al. | 2012
- 135
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A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOSShabany, M. / Gulak, P. G. et al. | 2012
- 148
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Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory ApplicationsShih-Fu Liu, / Reviriego, P. / Maestro, J. A. et al. | 2012
- 148
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Testing - Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory ApplicationsLiu, S-F et al. | 2012
- 157
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Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-FlopsHassan, F. / Vanderbauwhede, W. / Rodriguez-Salazar, F. et al. | 2012
- 157
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TRANSACTIONS BRIEFS - Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-FlopsFaiz-ul-Hassan, F et al. | 2012
- 162
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An Experimental Power-Lines Model for Digital ASICs Based on Transmission LinesCostagliola, M. / de Caro, D. / Girardi, A. / Izzi, R. / Rinaldi, N. / Spirito, M. / Spirito, P. et al. | 2012
- 167
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Power-Aware High-Level Synthesis With Clock Skew ManagementTung-Hua Yeh, / Sying-Jyan Wang, et al. | 2012
- 172
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Resolution of Diagnosis Based on Transition FaultsPomeranz, I. / Reddy, S. M. et al. | 2012
- 176
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Robust Secure Scan Design Against Scan-Based Differential CryptanalysisYouhua Shi, / Togawa, N. / Yanagisawa, M. / Ohtsuki, T. et al. | 2012
- 181
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A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)Jisu Kim, / Kyungho Ryu, / Kang, S. H. / Seong-Ook Jung, et al. | 2012
- 186
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Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICsXiaoxia Wu, / Wei Zhao, / Nakamoto, M. / Nimmagadda, C. / Lisk, D. / Gu, S. / Radojcic, R. / Nowak, M. / Yuan Xie, et al. | 2012
- 191
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ORION 2.0: A Power-Area Simulator for Interconnection NetworksKahng, A. B. / Bin Li, / Li-Shiuan Peh, / Samadi, K. et al. | 2012
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Table of contents| 2012
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2012
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2012