An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset (English)
- New search for: Rabuske, Taimur
- New search for: Rabuske, Taimur
- New search for: Rabuske, Fabio
- New search for: Fernandes, Jorge
- New search for: Rodrigues, Cesar
In:
IEEE transactions on very large scale integration (VLSI) systems
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23
, 7
; 1301-1307
;
2015
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ISSN:
- Article (Journal) / Print
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Title:An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 23, 7 ; 1301-1307
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2015
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DOI:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 53.52
- Further information on Basic classification
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Table of contents – Volume 23, Issue 7
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction EnvironmentKundu, Subhadip / Chattopadhyay, Santanu / Sengupta, Indranil / Kapur, Rohit et al. | 2015
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A Fault Detection and Tolerance Architecture for Post-Silicon Skew TuningKao, Mac Y. C. / Tsai, Kun-Ting / Chang, Shih-Chieh et al. | 2015
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PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit SynthesisLin, Chia-Chun / Sur-Kolay, Susmita / Jha, Niraj K. et al. | 2015
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An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting CapabilityYang, Chi-Heng / Lin, Yi-Min / Chang, Hsie-Chia / Lee, Chen-Yi et al. | 2015
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An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate ModelingYao, Jian / Ye, Zuochang / Wang, Yan et al. | 2015
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CACTI-IO: CACTI With OFF-Chip Power-Area-Timing ModelsJouppi, Norman P. / Kahng, Andrew B. / Muralimanohar, Naveen / Srinivas, Vaishnav et al. | 2015
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New Analytic Model of Coupling and Substrate Capacitance in Nanometer TechnologiesShomalnasab, Gholamreza / Zhang, Lihong et al. | 2015
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Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip PlatformsNeves, Nuno / Sebastiao, Nuno / Matos, David / Tomas, Pedro / Flores, Paulo / Roma, Nuno et al. | 2015
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An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator OffsetRabuske, Taimur / Rabuske, Fabio / Fernandes, Jorge / Rodrigues, Cesar et al. | 2015
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A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress ConsiderationsMarella, Sravan K. / Sapatnekar, Sachin S. et al. | 2015
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On the Efficacy of Through-Silicon-Via InductorsTida, Umamaheswara Rao / Yang, Rongbo / Zhuo, Cheng / Shi, Yiyu et al. | 2015
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Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital CommunicationXiu, Liming et al. | 2015
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Background Digital Calibration of Comparator Offsets in Pipeline ADCsGines, Antonio Jose / Peralias, Eduardo / Rueda, Adoracion et al. | 2015
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Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS ProcessZeng, Xiaoyang / Li, Yi / Zhang, Yuejun / Tan, Shujie / Han, Jun / Zhang, Xingxing / Zhang, Zhang / Cheng, Xu / Yu, Zhiyi et al. | 2015
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A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex OptimizationKim, Jintae / Lee, Minjae et al. | 2015
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Corrections to “Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction”Joshi, Rajiv V. / Kanj, Rouwaida et al. | 2015
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Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction" [Mar 15 534-543]Joshi, Rajiv V et al. | 2015
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Table of contents| 2015
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2015
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2015