Low power consumption arithmetic units in the 'Plastic Hard Macro Technology' (Japanese)
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In:
Transactions of the Information Processing Society of Japan
;
42
, 4
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1023-1029
;
2001
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ISSN:
- Article (Journal) / Print
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Title:Low power consumption arithmetic units in the 'Plastic Hard Macro Technology'
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Additional title:Titel japanisch
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Contributors:Taki, K. ( author ) / Kitamura, K. ( author )
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Published in:Transactions of the Information Processing Society of Japan ; 42, 4 ; 1023-1029
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Publisher:
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Publication date:2001
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Size:7 Seiten, 6 Quellen
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ISSN:
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Coden:
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Type of media:Article (Journal)
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Type of material:Print
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Language:Japanese
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Keywords:
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Source:
Table of contents – Volume 42, Issue 4
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 714
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Performance evaluation of adaptive routers based on the number of virtual channels and operating frequenciesHorita, M. / Yoshinagi, T. / Ootsu, K. / Baba, T. et al. | 2001
- 724
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Cost optimal parallel algorithms for the lexicographically first maximal 3 sum problem on the BSP modelNakashima, T. / Fujiwara, A. et al. | 2001
- 754
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Vectorized local search for CNF satisfiabilityKawai, D. / Miyazaki, S. / Okabe, Y. / Iwama, K. et al. | 2001
- 762
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Parallel processing of sparse Cholesky factorization by generalized skyline methodMiyakawa, Y. / Matsuda, A. / Kato, T. et al. | 2001
- 802
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The performance evaluation of Omni OpenMP compilerKusano, K. / Satoh, S. / Sato, M. et al. | 2001
- 868
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Communication generation for data-parallel languages and evaluation of optimizations with the multigrid methodOhta, H. / Nishitani, N. et al. | 2001
- 930
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The recent status and future trends of embedded system development technologyTakada, H. et al. | 2001
- 939
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VLSI implementation of fractal image compression processor for moving picturesYamauchi, H. / Takeuchi, Y. / Imai, M. et al. | 2001
- 950
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An architecture for secure encryption VLSI processors using a constant-characteristic power dissipation conceptMatsubara, H. / Watanabe, T. / Nakamura, T. et al. | 2001
- 958
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A novel dynamically reconfigurable hardware-based cipherAndales, Z. / Mitsuyama, Y. / Onoya, T. / Shirakawa, I. et al. | 2001
- 967
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Synthesis of low power circuits combining CMOS/pass transistor logicTakata, E. / Jinno, C. / Kuroki, N. / Numa, M. / Taki, K. / Yamamoto, K. et al. | 2001
- 992
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Fixed-polarity OR-AND-EXOR expressions and their minimizationHirayama, T. / Nagasawa, K. / Shimizu, K. et al. | 2001
- 1007
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A design method for low power arithmetic circuits considering input patternsMuroyama, M. / Ishihara, T. / Hyodo, A. / Yasuura, H. et al. | 2001
- 1023
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Low power consumption arithmetic units in the 'Plastic Hard Macro Technology'Taki, K. / Kitamura, K. et al. | 2001
- 1054
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RTL partial scan design system: REPSYoshimura, M. / Hosokawa, T. / Ohta, M. et al. | 2001